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LDAEXD -- AArch32

LDAEXD

Load-Acquire Exclusive Doubleword loads a doubleword from memory, writes it to two registers and:

The instruction also acts as a barrier instruction with the ordering requirements described in Load-Acquire, Store-Release.

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100011011RnRt(1)(1)101001(1)(1)(1)(1)
condsizeLexordxRt

Encoding

LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]

Decode for this encoding

let t : integer = UInt(Rt); let t2 : integer = t + 1; let n : integer = UInt(Rn); if Rt[0] == '1' || t2 == 15 || n == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If Rt<0> == '1', then one of the following behaviors must occur:

If Rt == '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111010001101RnRtRt21111(1)(1)(1)(1)
op0LopszRd

Encoding

LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]

Decode for this encoding

let t : integer = UInt(Rt); let t2 : integer = UInt(Rt2); let n : integer = UInt(Rn); if t == 15 || t2 == 15 || t == t2 || n == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If t == t2, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rt>

For the "A1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt> must be even-numbered and not R14.

For the "T1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field.

<Rt2>

For the "A1" variant: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

For the "T1" variant: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n); AArch32_SetExclusiveMonitors(address, 8); let value : bits(64) = MemO{64}(address); // Extract words from 64-bit loaded value such that R[t] is // loaded from address and R[t2] from address+4. R(t) = if BigEndian(AccessType_GPR) then value[63:32] else value[31:0]; R(t2) = if BigEndian(AccessType_GPR) then value[31:0] else value[63:32]; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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