LDMIB, LDMED -- AArch32

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LDMIB, LDMED

Load Multiple Increment Before (Empty Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register.

The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register from the highest memory address. See also Encoding of lists of general-purpose registers and the PC.

Armv8.2 permits the deprecation of some Load Multiple ordering behaviors in AArch32 state, for more information see FEAT_LSMAOC. The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. Related system instructions are LDM (User registers) and LDM (exception return).

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				1	0	0	1	1	0	W	1	Rn				register_list
cond							P	U	op		L

Encoding

LDMIB{<c>}{<q>} <Rn>{!}, <registers> // (Preferred syntax)

LDMED{<c>}{<q>} <Rn>{!}, <registers> // (Alternate syntax, Empty Descending stack)

Decode for this encoding

let n : integer = UInt(Rn); let registers : bits(16) = register_list; let wback : boolean = (W == '1'); if n == 15 || BitCount(registers) < 1 then UnpredictableProcedure(); end; if wback && registers[n] == '1' then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If BitCount(registers) < 1, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction operates as an LDM with the same addressing mode but targeting an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.

If wback && registers<n> == '1', then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction performs all of the loads using the specified addressing mode and the content of the register that is written back is UNKNOWN. In addition, if an exception occurs during such as instruction, the base address might be corrupted so that the instruction cannot be repeated.

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

!	The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.

Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }.

The PC can be in the list.

Arm deprecates using these instructions with both the LR and the PC in the list.

Operation

if ConditionPassed() then EncodingSpecificOperations(); var address : bits(32) = R(n) + 4; var data : bits(32); for i = 0 to 14 do if registers[i] == '1' then if i != n then R(i) = MemS{32}(address); else data = MemS{32}(address); end; address = address + 4; end; end; if registers[15] == '1' then LoadWritePC(MemS{32}(address)); end; if wback && registers[n] == '1' then R(n) = ARBITRARY : bits(32); end; if wback && registers[n] == '0' then R(n) = R(n) + 4*BitCount(registers); end; if !wback && registers[n] == '1' then R(n) = data; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2026-03_rel 2026-03-26 20:48:11