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LDREX -- AArch32

LDREX

Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and:

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100011001RnRt(1)(1)111001(1)(1)(1)(1)
condsizeLexordxRt

Encoding

LDREX{<c>}{<q>} <Rt>, [<Rn> {, {#}<imm>}]

Decode for this encoding

let t : integer = UInt(Rt); let n : integer = UInt(Rn); let imm32 : bits(32) = Zeros{}; // Zero offset if t == 15 || n == 15 then UnpredictableProcedure(); end;

T1

15141312111098765432101514131211109876543210
111010000101RnRt(1)(1)(1)(1)imm8
op0LRd

Encoding

LDREX{<c>}{<q>} <Rt>, [<Rn> {, #<imm>}]

Decode for this encoding

let t : integer = UInt(Rt); let n : integer = UInt(Rn); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); // Armv8-A removes UNPREDICTABLE for R13 if t == 15 || n == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rt>

Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field.

<imm>

For the "A1" variant: the immediate offset added to the value of <Rn> to calculate the address. <imm> can only be 0 or omitted.

For the "T1" variant: the immediate offset added to the value of <Rn> to calculate the address. <imm> can be omitted, meaning an offset of 0. Values are multiples of 4 in the range 0-1020.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n) + imm32; AArch32_SetExclusiveMonitors(address,4); R(t) = MemA{32}(address); end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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