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MRS -- AArch32

MRS

Move Special register to general-purpose register moves the value of the APSR, CPSR, or SPSR_<current_mode> into a general-purpose register.

Arm recommends the APSR form when only the N, Z, C, V, Q, and GE[3:0] bits are being written. For more information, see APSR.

An MRS that accesses the SPSRs is UNPREDICTABLE if executed in User mode or System mode.

An MRS that is executed in User mode and accesses the CPSR returns an UNKNOWN value for the CPSR.{E, A, I, F, M} fields.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100010R00(1)(1)(1)(1)Rd(0)(0)0(0)0000(0)(0)(0)(0)
condmaskBmRn

Encoding

MRS{<c>}{<q>} <Rd>, <spec_reg>

Decode for this encoding

let d : integer = UInt(Rd); let read_spsr : boolean = (R == '1'); if d == 15 then UnpredictableProcedure(); end;

T1

15141312111098765432101514131211109876543210
11110011111R(1)(1)(1)(1)10(0)0Rd(0)(0)0(0)(0)(0)(0)(0)

Encoding

MRS{<c>}{<q>} <Rd>, <spec_reg>

Decode for this encoding

let d : integer = UInt(Rd); let read_spsr : boolean = (R == '1'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<spec_reg>

Is the special register to be accessed, encoded in R:

R <spec_reg>
0 CPSR|APSR
1 SPSR

Operation

if ConditionPassed() then EncodingSpecificOperations(); if read_spsr then if PSTATE.M IN {M32_User,M32_System} then UnpredictableProcedure(); else R(d) = SPSR_curr(); end; else // CPSR has same bit assignments as SPSR, but with the IT, J, SS, IL, and T bits masked out. let maskval : bits(32) = '11111000 11101111 00000011 11011111'; var psr_val : bits(32) = GetPSRFromPSTATE{32}(AArch32_NonDebugState) AND maskval; if PSTATE.EL == EL0 then // If accessed from User mode return UNKNOWN values for E, A, I, F bits, bits<9:6>, // and for the M field, bits<4:0> psr_val[22] = ARBITRARY : bits(1); psr_val[9:6] = ARBITRARY : bits(4); psr_val[4:0] = ARBITRARY : bits(5); end; R(d) = psr_val; end; end;

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.M IN {M32_User, M32_System} && read_spsr, then one of the following behaviors must occur:


2026-03_rel 2026-03-26 20:48:11

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