PUSH -- AArch32

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PUSH -- AArch32

PUSH

Push Multiple Registers to Stack stores multiple general-purpose registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data.

The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to the highest memory address. See also Encoding of lists of general-purpose registers and the PC.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	0	1	1	0	1	0	M	register_list
				L

Encoding

PUSH{<c>}{<q>} <registers> // (Preferred syntax)

STMDB{<c>}{<q>} SP!, <registers> // (Alternate syntax)

Decode for this encoding

let registers : bits(16) = '0'::M::'000000'::register_list; let UnalignedAllowed : boolean = FALSE; if BitCount(registers) < 1 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If BitCount(registers) < 1, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction targets an unspecified set of registers. These registers might include R15. If the instruction specifies writeback, the modification to the base address on writeback might differ from the number of registers loaded.

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

Is a list of one or more registers to be stored, separated by commas and surrounded by { and }.

The registers in the list must be in the range R0-R7, encoded in the "register_list" field, and can optionally include the LR. If the LR is in the list, the "M" field is set to 1, otherwise this field defaults to 0.

Operation

if ConditionPassed() then EncodingSpecificOperations(); var address : bits(32) = R(13) - 4*BitCount(registers); for i = 0 to 14 do if registers[i] == '1' then if i == 13 && i != LowestSetBit(registers) then // Only possible for encoding A1 MemA{32}(address) = ARBITRARY : bits(32); else if UnalignedAllowed then MemU{32}(address) = R(i); else MemA{32}(address) = R(i); end; end; address = address + 4; end; end; if registers[15] == '1' then // Only possible for encoding A1 or A2 if UnalignedAllowed then MemU{32}(address) = PCStoreValue(); else MemA{32}(address) = PCStoreValue(); end; end; R(13) = R(13) - 4*BitCount(registers); end;

2026-03_rel 2026-03-26 20:48:11