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REV16 -- AArch32

REV16

Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111101101011(1)(1)(1)(1)Rd(1)(1)(1)(1)1011Rm
condo1o2

Encoding

REV16{<c>}{<q>} <Rd>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); if d == 15 || m == 15 then UnpredictableProcedure(); end;

T1

1514131211109876543210
1011101001RmRd
op

Encoding

REV16{<c>}{<q>} <Rd>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm);

T2

15141312111098765432101514131211109876543210
111110101001Rn1111Rd1001Rm
op1op2

Encoding

REV16{<c>}{<q>} <Rd>, <Rm>

REV16{<c>}.W <Rd>, <Rm> // (<Rd>, <Rm> can be represented in T1)

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); let n : integer = UInt(Rn); // Armv8-A removes UNPREDICTABLE for R13 if m != n || d == 15 || m == 15 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If m != n, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

For the "A1" and "T1" variants: is the general-purpose source register, encoded in the "Rm" field.

For the "T2" variant: is the general-purpose source register, encoded in the "Rm" field. It must be encoded with an identical value in the "Rn" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); var result : bits(32); result[31:24] = R(m)[23:16]; result[23:16] = R(m)[31:24]; result[15:8] = R(m)[7:0]; result[7:0] = R(m)[15:8]; R(d) = result; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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