This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

SADD8 -- AArch32

SADD8

Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets PSTATE.GE according to the results of the additions.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111101100001RnRd(1)(1)(1)(1)1001Rm
condop1Bop2

Encoding

SADD8{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

15141312111098765432101514131211109876543210
111110101000Rn1111Rd0000Rm
op1UHS

Encoding

SADD8{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>

Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>

Is the second general-purpose source register, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let sum1 : integer = SInt(R(n)[7:0]) + SInt(R(m)[7:0]); let sum2 : integer = SInt(R(n)[15:8]) + SInt(R(m)[15:8]); let sum3 : integer = SInt(R(n)[23:16]) + SInt(R(m)[23:16]); let sum4 : integer = SInt(R(n)[31:24]) + SInt(R(m)[31:24]); R(d)[7:0] = sum1[7:0]; R(d)[15:8] = sum2[7:0]; R(d)[23:16] = sum3[7:0]; R(d)[31:24] = sum4[7:0]; PSTATE.GE[0] = if sum1 >= 0 then '1' else '0'; PSTATE.GE[1] = if sum2 >= 0 then '1' else '0'; PSTATE.GE[2] = if sum3 >= 0 then '1' else '0'; PSTATE.GE[3] = if sum4 >= 0 then '1' else '0'; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.