SMLABB, SMLABT, SMLATB, SMLATT -- AArch32

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SMLABB, SMLABT, SMLATB, SMLATT

Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register.

If overflow occurs during the addition of the accumulate value, the instruction sets PSTATE.Q to 1. It is not possible for overflow to occur during the multiplication.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	0	0	0	0	Rd				Ra				Rm				1	M	N	0	Rn
cond									opc

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let a : integer = UInt(Ra); let n_index : integer = UInt(N); let m_index : integer = UInt(M); if d == 15 || n == 15 || m == 15 || a == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	0	0	0	1	Rn				!= 1111				Rd				0	0	N	M	Rm
									op1							Ra

Encoding for the SMLABB variant

Applies when (N == 0 && M == 0)

SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Encoding for the SMLABT variant

Applies when (N == 0 && M == 1)

SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Encoding for the SMLATB variant

Applies when (N == 1 && M == 0)

SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Encoding for the SMLATT variant

Applies when (N == 1 && M == 1)

SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>

Decode for all variants of this encoding

if Ra == '1111' then See("SMULBB, SMULBT, SMULTB, SMULTT"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let a : integer = UInt(Ra); let n_index : integer = UInt(N); let m_index : integer = UInt(M); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <x>), encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <y>), encoded in the "Rm" field.

<Ra>	Is the third general-purpose source register holding the addend, encoded in the "Ra" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let operand1 : bits(16) = R(n)[n_index*:16]; let operand2 : bits(16) = R(m)[m_index*:16]; let result : integer = SInt(operand1) * SInt(operand2) + SInt(R(a)); R(d) = result[31:0]; if result != SInt(result[31:0]) then // Signed overflow PSTATE.Q = '1'; end; end;

2026-03_rel 2026-03-26 20:48:11