SMLAL, SMLALS -- AArch32

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SMLAL, SMLALS

Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value.

In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many implementations.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	0	1	1	1	S	RdHi				RdLo				Rm				1	0	0	1	Rn
cond								opc

Encoding for the Flag setting variant

Applies when (S == 1)

SMLALS{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>

Encoding for the Not flag setting variant

Applies when (S == 0)

SMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>

Decode for all variants of this encoding

let dLo : integer = UInt(RdLo); let dHi : integer = UInt(RdHi); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let setflags : boolean = (S == '1'); if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end; if dHi == dLo then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If dHi == dLo, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The value in the destination register is unknown.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	1	1	0	0	Rn				RdLo				RdHi				0	0	0	0	Rm
									op1															op2

Encoding

SMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>

Decode for this encoding

let dLo : integer = UInt(RdLo); let dHi : integer = UInt(RdHi); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let setflags : boolean = FALSE; if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end; // Armv8-A removes UNPREDICTABLE for R13 if dHi == dLo then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If dHi == dLo, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The value in the destination register is unknown.

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<RdLo>

Is the general-purpose source register holding the lower 32 bits of the addend, and the destination register for the lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>

Is the general-purpose source register holding the upper 32 bits of the addend, and the destination register for the upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>	Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let result : integer = SInt(R(n)) * SInt(R(m)) + SInt(R(dHi)::R(dLo)); R(dHi) = result[63:32]; R(dLo) = result[31:0]; if setflags then PSTATE.N = result[63]; PSTATE.Z = IsZeroBit{64}(result[63:0]); // PSTATE.C, PSTATE.V unchanged end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2026-03_rel 2026-03-26 20:48:11