This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

SMMUL, SMMULR -- AArch32

SMMUL, SMMULR

Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register.

Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111101110101Rd1111Rm00R1Rn
condop1Ra

Encoding for the SMMUL variant

Applies when (R == 0)

SMMUL{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Encoding for the SMMULR variant

Applies when (R == 1)

SMMULR{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let round : boolean = (R == '1'); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

15141312111098765432101514131211109876543210
111110110101Rn1111Rd000RRm
op1Ra

Encoding for the SMMUL variant

Applies when (R == 0)

SMMUL{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Encoding for the SMMULR variant

Applies when (R == 1)

SMMULR{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let round : boolean = (R == '1'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>

Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>

Is the second general-purpose source register, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); var result : integer = SInt(R(n)) * SInt(R(m)); if round then result = result + 0x80000000; end; R(d) = result[63:32]; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.