SMULBB, SMULBT, SMULTB, SMULTT -- AArch32

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SMULBB, SMULBT, SMULTB, SMULTT

Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	0	1	1	0	Rd				(0)	(0)	(0)	(0)	Rm				1	M	N	0	Rn
cond									opc							Ra

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let n_index : integer = UInt(N); let m_index : integer = UInt(M); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	0	0	0	1	Rn				1	1	1	1	Rd				0	0	N	M	Rm
									op1							Ra

Encoding for the SMULBB variant

Applies when (N == 0 && M == 0)

SMULBB{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Encoding for the SMULBT variant

Applies when (N == 0 && M == 1)

SMULBT{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Encoding for the SMULTB variant

Applies when (N == 1 && M == 0)

SMULTB{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Encoding for the SMULTT variant

Applies when (N == 1 && M == 1)

SMULTT{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); let n_index : integer = UInt(N); let m_index : integer = UInt(M); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the first general-purpose source register holding the multiplicand in the bottom or top half (selected by <x>), encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register holding the multiplier in the bottom or top half (selected by <y>), encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let operand1 : bits(16) = R(n)[n_index*:16]; let operand2 : bits(16) = R(m)[m_index*:16]; let result : integer = SInt(operand1) * SInt(operand2); R(d) = result[31:0]; // Signed overflow cannot occur end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2026-03_rel 2026-03-26 20:48:11

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	0	0	0	1	Rn				1	1	1	1	Rd				0	0	N	M	Rm
									op1							Ra

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	0	0	0	1	Rn				1	1	1	1	Rd				0	0	N	M	Rm
									op1							Ra

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	1	0	0	0	1	Rn				1	1	1	1	Rd				0	0	N	M	Rm
									op1							Ra