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SRS, SRSDA, SRSDB, SRSIA, SRSIB -- AArch32
Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

SRS, SRSDA, SRSDB, SRSIA, SRSIB

Store Return State stores the LR_<current_mode> and SPSR_<current_mode> to the stack of a specified mode. For information about memory accesses see Memory accesses.

SRS is UNDEFINED in Hyp mode.

SRS is CONSTRAINED UNPREDICTABLE if it is executed in User or System mode, or if the specified mode is any of the following:

If EL3 is using AArch64 and an SRS instruction that is executed in a Secure EL1 mode specifies Monitor mode, it is trapped to EL3.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
1111100PU1W0(1)(1)(0)(1)(0)(0)(0)(0)(0)(1)(0)(1)(0)(0)(0)mode
SLRnop

Encoding for the Decrement After variant

Applies when (P == 0 && U == 0)

SRSDA{<c>}{<q>} SP{!}, #<mode>

Encoding for the Decrement Before variant

Applies when (P == 1 && U == 0)

SRSDB{<c>}{<q>} SP{!}, #<mode>

Encoding for the Increment After variant

Applies when (P == 0 && U == 1)

SRS{IA}{<c>}{<q>} SP{!}, #<mode>

Encoding for the Increment Before variant

Applies when (P == 1 && U == 1)

SRSIB{<c>}{<q>} SP{!}, #<mode>

Decode for all variants of this encoding

let wback : boolean = (W == '1'); let increment : boolean = (U == '1'); let wordhigher : boolean = (P == U);

T1

15141312111098765432101514131211109876543210
1110100000W0(1)(1)(0)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)mode
opcLRnPM

Encoding

SRSDB{<c>}{<q>} SP{!}, #<mode>

Decode for this encoding

let wback : boolean = (W == '1'); let increment : boolean = FALSE; let wordhigher : boolean = FALSE;

T2

15141312111098765432101514131211109876543210
1110100110W0(1)(1)(0)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)(0)mode
opcLRnPM

Encoding

SRS{IA}{<c>}{<q>} SP{!}, #<mode>

Decode for this encoding

let wback : boolean = (W == '1'); let increment : boolean = TRUE; let wordhigher : boolean = FALSE;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly SRS (T32) and SRS (A32).

Assembler Symbols

<c>

For the "Decrement After", "Decrement Before", "Increment After", and "Increment Before" variants: see Standard assembler syntax fields. <c> must be AL or omitted.

For the "T1" and "T2" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

!

The address adjusted by the size of the data loaded is written back to the base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<mode>

Is the number of the mode whose Banked SP is used as the base register, encoded in the "mode" field. For details of PE modes and their numbers see AArch32 state PE modes.

IA

For the "Increment After" variant: is an optional suffix to indicate the Increment After variant.

For the "T2" variant: is an optional suffix for the Increment After form.

SRSFA, SRSEA, SRSFD, and SRSED are pseudo-instructions for SRSIB, SRSIA, SRSDB, and SRSDA respectively, referring to their use for pushing data onto Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.

Operation

if CurrentInstrSet() == InstrSet_A32 then if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then // UNDEFINED at EL2 Undefined(); end; // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these // to be security holes if PSTATE.M IN {M32_User,M32_System} then UnpredictableProcedure(); elsif mode == M32_Hyp then // Check for attempt to access Hyp mode SP UnpredictableProcedure(); elsif mode == M32_Monitor then // Check for attempt to access Monitor mode SP if !HaveEL(EL3) || CurrentSecurityState() != SS_Secure then UnpredictableProcedure(); elsif !ELUsingAArch32(EL3) then AArch64_MonitorModeTrap(); end; elsif BadMode(mode) then UnpredictableProcedure(); end; let base : bits(32) = Rmode(13,mode); var address : bits(32) = if increment then base else base-8; if wordhigher then address = address+4; end; MemA{32}(address) = LR(); MemA{32}(address+4) = SPSR_curr(); if wback then Rmode(13,mode) = if increment then base+8 else base-8; end; end; else if ConditionPassed() then EncodingSpecificOperations(); if PSTATE.EL == EL2 then // UNDEFINED at EL2 Undefined(); end; // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these // to be security holes if PSTATE.M IN {M32_User,M32_System} then UnpredictableProcedure(); elsif mode == M32_Hyp then // Check for attempt to access Hyp mode SP UnpredictableProcedure(); elsif mode == M32_Monitor then // Check for attempt to access Monitor mode SP if !HaveEL(EL3) || CurrentSecurityState() != SS_Secure then UnpredictableProcedure(); elsif !ELUsingAArch32(EL3) then AArch64_MonitorModeTrap(); end; elsif BadMode(mode) then UnpredictableProcedure(); end; let base : bits(32) = Rmode(13,mode); var address : bits(32) = if increment then base else base-8; if wordhigher then address = address+4; end; MemA{32}(address) = LR(); MemA{32}(address+4) = SPSR_curr(); if wback then Rmode(13,mode) = if increment then base+8 else base-8; end; end; end;

CONSTRAINED UNPREDICTABLE behavior

If PSTATE.M IN {M32_User,M32_System}, then one of the following behaviors must occur:

If mode == M32_Hyp, then one of the following behaviors must occur:

If mode == M32_Monitor && (!HaveEL(EL3) || CurrentSecurityState() != SS_Secure), then one of the following behaviors must occur:

If BadMode(mode), then one of the following behaviors must occur:

Base Instructions
SIMD&FP Instructions
A32 Instructions by Encoding
T32 Instructions by Encoding
Shared Pseudocode
Proprietary Notice

2026-03_rel 2026-03-26 20:48:11

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