SSAT -- AArch32

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SSAT -- AArch32

SSAT

Signed Saturate saturates an optionally-shifted signed value to a selectable signed range.

This instruction sets PSTATE.Q to 1 if the operation saturates.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	0	1	0	1	sat_imm					Rd				imm5					sh	0	1	Rn
cond									U

Encoding for the Arithmetic shift right variant

Applies when (sh == 1)

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount>

Encoding for the Logical shift left variant

Applies when (sh == 0)

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount>}

Decode for all variants of this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let saturate_to : integer{} = UInt(sat_imm)+1; let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(sh::'0', imm5); if d == 15 || n == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	0	(0)	1	1	0	0	sh	0	Rn				0	imm3			Rd				imm2		(0)	sat_imm

Encoding for the Arithmetic shift right variant

Applies when (sh == 1 && !(imm3 == 000 && imm2 == 00))

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount>

Encoding for the Logical shift left variant

Applies when (sh == 0)

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount>}

Decode for all variants of this encoding

if sh == '1' && (imm3::imm2) == '00000' then See("SSAT16"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let saturate_to : integer{} = UInt(sat_imm)+1; let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(sh::'0', imm3::imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<imm>

Is the bit position for saturation, in the range 1 to 32, encoded in the "sat_imm" field as <imm>-1.

<Rn>	Is the general-purpose source register, encoded in the "Rn" field.

<amount>	For the "A1 Arithmetic shift right" variant: is the shift amount, in the range 1 to 32 encoded in the "imm5" field as <amount> modulo 32.
	For the "A1 Logical shift left" variant: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm5" field.
	For the "T1 Arithmetic shift right" variant: is the shift amount, in the range 1 to 31 encoded in the "imm3:imm2" field as <amount>.
	For the "T1 Logical shift left" variant: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm3:imm2" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let operand : bits(32) = Shift{}(R(n), shift_t, shift_n, PSTATE.C); // PSTATE.C ignored let (result, sat) : (bits(saturate_to), boolean) = SignedSatQ{saturate_to}(SInt(operand)); R(d) = SignExtend{32}(result); if sat then PSTATE.Q = '1'; end; end;

2026-03_rel 2026-03-26 20:48:11