This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

STLEXD -- AArch32

STLEXD

Store-Release Exclusive Doubleword stores a doubleword from two registers to memory if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release.

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111100011010RnRd(1)(1)101001Rt
condsizeLexord

Encoding

STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]

Decode for this encoding

let t : integer = UInt(Rt); let t2 : integer = t + 1; let d : integer = UInt(Rd); let n : integer = UInt(Rn); if d == 15 || Rt[0] == '1' || t2 == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t || d == t2 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If d == t, then one of the following behaviors must occur:

If d == n, then one of the following behaviors must occur:

If Rt<0> == '1', then one of the following behaviors must occur:

If Rt == '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111010001100RnRtRt21111Rd
op0Lopsz

Encoding

STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]

Decode for this encoding

let d : integer = UInt(Rd); let t : integer = UInt(Rt); let t2 : integer = UInt(Rt2); let n : integer = UInt(Rn); if d == 15 || t == 15 || t2 == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t || d == t2 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If d == t, then one of the following behaviors must occur:

If d == n, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is:

0
If the operation updates memory.
1
If the operation fails to update memory.
<Rt>

For the "A1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field. <Rt> must be even-numbered and not R14.

For the "T1" variant: is the first general-purpose register to be transferred, encoded in the "Rt" field.

<Rt2>

For the "A1" variant: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

For the "T1" variant: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Rn>

Is the general-purpose base register, encoded in the "Rn" field.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n); // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4. let value : bits(64) = if BigEndian(AccessType_GPR) then R(t)::R(t2) else R(t2)::R(t); if AArch32_ExclusiveMonitorsPass(address, 8) then MemO{64}(address) = value; R(d) = ZeroExtend{32}('0'); else R(d) = ZeroExtend{32}('1'); end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.