STREXH -- AArch32

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STREXH -- AArch32

STREXH

Store Register Exclusive Halfword derives an address from a base register value, stores a halfword from a register to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed.

For more information about support for shared memory see Synchronization and semaphores. For information about memory accesses see Memory accesses.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	0	0	1	1	1	1	0	Rn				Rd				(1)	(1)	1	1	1	0	0	1	Rt
cond									size		L											ex	ord

Encoding

STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]

Decode for this encoding

let d : integer = UInt(Rd); let t : integer = UInt(Rt); let n : integer = UInt(Rn); if d == 15 || t == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If d == t, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The store instruction executes but the value stored is unknown.

If d == n, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction performs the store to an UNKNOWN address.

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	0	1	1	0	0	Rn				Rt				(1)	(1)	(1)	(1)	0	1	0	1	Rd
							op0				L									Rt2						sz

Encoding

STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]

Decode for this encoding

let d : integer = UInt(Rd); let t : integer = UInt(Rt); let n : integer = UInt(Rn); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || t == 15 || n == 15 then UnpredictableProcedure(); end; if d == n || d == t then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If d == t, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The store instruction executes but the value stored is unknown.

If d == n, then one of the following behaviors must occur:

The instruction is undefined.
The instruction executes as NOP.
The instruction performs the store to an UNKNOWN address.

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the destination general-purpose register into which the status result of the store exclusive is written, encoded in the "Rd" field. The value returned is: 0 If the operation updates memory. 1 If the operation fails to update memory.

<Rt>	Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>	Is the general-purpose base register, encoded in the "Rn" field.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

Memory is not updated.
<Rd> is not updated.

A non halfword-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:

If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.
Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let address : bits(32) = R(n); if AArch32_ExclusiveMonitorsPass(address,2) then MemA{16}(address) = R(t)[15:0]; R(d) = ZeroExtend{32}('0'); else R(d) = ZeroExtend{32}('1'); end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2026-03_rel 2026-03-26 20:48:11

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	0	1	1	0	0	Rn				Rt				(1)	(1)	(1)	(1)	0	1	0	1	Rd
							op0				L									Rt2						sz

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	0	1	1	0	0	Rn				Rt				(1)	(1)	(1)	(1)	0	1	0	1	Rd
							op0				L									Rt2						sz

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	1	0	0	0	1	1	0	0	Rn				Rt				(1)	(1)	(1)	(1)	0	1	0	1	Rd
							op0				L									Rt2						sz