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SXTB -- AArch32

SXTB

Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 1111011010101111Rdrotate(0)(0)0111Rm
condUopRn

Encoding

SXTB{<c>}{<q>} {<Rd>, }<Rm> {, ROR #<amount>}

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); let rotation : integer = UInt(rotate::'000'); if d == 15 || m == 15 then UnpredictableProcedure(); end;

T1

1514131211109876543210
1011001001RmRd
UB

Encoding

SXTB{<c>}{<q>} {<Rd>, }<Rm>

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); let rotation : integer = 0;

T2

15141312111098765432101514131211109876543210
11111010010011111111Rd1(0)rotateRm
op1URn

Encoding

SXTB{<c>}{<q>} {<Rd>, }<Rm> {, ROR #<amount>}

SXTB{<c>}.W {<Rd>, }<Rm> // (<Rd>, <Rm> can be represented in T1)

Decode for this encoding

let d : integer = UInt(Rd); let m : integer = UInt(Rm); let rotation : integer = UInt(rotate::'000'); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>

Is the general-purpose source register, encoded in the "Rm" field.

<amount>

Is the rotate amount, encoded in rotate:

rotate <amount>
00 [absent]
01 8
10 16
11 24

Operation

if ConditionPassed() then EncodingSpecificOperations(); let rotated : bits(32) = ROR(R(m), rotation); R(d) = SignExtend{32}(rotated[7:0]); end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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