This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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TSB

Trace Synchronization Barrier. This instruction is a barrier that synchronizes the trace operations of instructions, see Trace Synchronization Barrier (TSB).

If FEAT_TRF is not implemented, this instruction executes as a NOP.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1
(FEAT_TRF)

Decode for this encoding

if !IsFeatureImplemented(FEAT_TRF) then ExecuteAsNOP(); end; if cond != '1110' then UnpredictableProcedure(); end; // TSB must be encoded with AL condition

CONSTRAINED UNPREDICTABLE behavior

If cond != '1110', then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes unconditionally.
• The instruction executes conditionally.

T1
(FEAT_TRF)

Decode for this encoding

if !IsFeatureImplemented(FEAT_TRF) then ExecuteAsNOP(); end; if InITBlock() then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If InITBlock(), then one of the following behaviors must occur:

• The instruction is undefined.
• The instruction executes as NOP.
• The instruction executes unconditionally.
• The instruction executes conditionally.