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UBFX -- AArch32

UBFX

Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 11110111111widthm1Rdlsb101Rn
condU

Encoding

UBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let lsbit : integer{} = UInt(lsb); let widthminus1 : integer{} = UInt(widthm1); let msbit : integer{} = lsbit + widthminus1; if d == 15 || n == 15 then UnpredictableProcedure(); end; if msbit > 31 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If msbit > 31, then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
11110(0)111100Rn0imm3Rdimm2(0)widthm1
op1

Encoding

UBFX{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let lsbit : integer{} = UInt(imm3::imm2); let widthminus1 : integer{} = UInt(widthm1); let msbit : integer{} = lsbit + widthminus1; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 then UnpredictableProcedure(); end; if msbit > 31 then UnpredictableProcedure(); end;

CONSTRAINED UNPREDICTABLE behavior

If msbit > 31, then one of the following behaviors must occur:

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Rd>

Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>

Is the general-purpose source register, encoded in the "Rn" field.

<lsb>

For the "A1" variant: is the bit number of the least significant bit in the field, in the range 0 to 31, encoded in the "lsb" field.

For the "T1" variant: is the bit number of the least significant bit in the field, in the range 0 to 31, encoded in the "imm3:imm2" field.

<width>

Is the width of the field, in the range 1 to 32-<lsb>, encoded in the "widthm1" field as <width>-1.

Operation

if ConditionPassed() then EncodingSpecificOperations(); R(d) = ZeroExtend{32}(R(n)[msbit:lsbit]); end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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