UHSUB16 -- AArch32

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UHSUB16 -- AArch32

UHSUB16

Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
!= 1111				0	1	1	0	0	1	1	1	Rn				Rd				(1)	(1)	(1)	(1)	0	1	1	1	Rm
cond									op1															B	op2

Encoding

UHSUB16{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

T1

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	0	1	1	0	1	Rn				1	1	1	1	Rd				0	1	1	0	Rm
									op1																U	H	S

Encoding

UHSUB16{<c>}{<q>} {<Rd>, }<Rn>, <Rm>

Decode for this encoding

let d : integer = UInt(Rd); let n : integer = UInt(Rn); let m : integer = UInt(Rm); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>	See Standard assembler syntax fields.

<q>	See Standard assembler syntax fields.

<Rd>	Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>	Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>	Is the second general-purpose source register, encoded in the "Rm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); let diff1 : integer = UInt(R(n)[15:0]) - UInt(R(m)[15:0]); let diff2 : integer = UInt(R(n)[31:16]) - UInt(R(m)[31:16]); R(d)[15:0] = diff1[16:1]; R(d)[31:16] = diff2[16:1]; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.

2026-03_rel 2026-03-26 20:48:11

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	0	1	1	0	1	Rn				1	1	1	1	Rd				0	1	1	0	Rm
									op1																U	H	S

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	0	1	1	0	1	Rn				1	1	1	1	Rd				0	1	1	0	Rm
									op1																U	H	S

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	0	1	0	1	1	0	1	Rn				1	1	1	1	Rd				0	1	1	0	Rm
									op1																U	H	S