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VABA -- AArch32

VABA

Vector Absolute Difference and Accumulate subtracts the elements of one vector from the corresponding elements of another vector, and accumulates the absolute values of the results into the elements of the destination vector.

Operand and result elements are all integers of the same length.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001U0DsizeVnVd0111NQM1Vm
opco1

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VABA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VABA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm>

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; let unsigned : boolean = (U == '1'); let long_destination : boolean = FALSE; let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize; let regs : integer = if Q == '0' then 1 else 2;

T1

15141312111098765432101514131211109876543210
111U11110DsizeVnVd0111NQM1Vm
opco1

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VABA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VABA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm>

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vn[0] == '1' || Vm[0] == '1') then Undefined(); end; let unsigned : boolean = (U == '1'); let long_destination : boolean = FALSE; let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize; let regs : integer = if Q == '0' then 1 else 2;

Assembler Symbols

<c>

For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the operands, encoded in (U :: size):

U size <dt>
0 00 S8
0 01 S16
0 10 S32
1 00 U8
1 01 U16
1 10 U32
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>

Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>

Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qn>

Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>

Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for r = 0 to regs-1 do for e = 0 to elements-1 do let op1elt : bits(esize) = Din(n+r)[e*:esize]; let op2elt : bits(esize) = Din(m+r)[e*:esize]; let element1 : integer = if unsigned then UInt(op1elt) else SInt(op1elt); let element2 : integer = if unsigned then UInt(op2elt) else SInt(op2elt); let absdiff : integer = Abs(element1 - element2); if long_destination then Q(d>>1)[e*:(2*esize)] = Qin(d>>1)[e*:(2*esize)] + absdiff; else D(d+r)[e*:esize] = Din(d+r)[e*:esize] + absdiff; end; end; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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