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VADDHN

Vector Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and places the most significant half of each result in a doubleword vector. The results are truncated. For rounded results, see VRADDHN.

The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned integers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for this encoding

if size == '11' then See("Related encodings"); end; if Vn[0] == '1' || Vm[0] == '1' then Undefined(); end; let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize;

T1

Decode for this encoding

if size == '11' then See("Related encodings"); end; if Vn[0] == '1' || Vm[0] == '1' then Undefined(); end; let esize : integer{} = 8 << UInt(size); let d : integer = UInt(D::Vd); let n : integer = UInt(N::Vn); let m : integer = UInt(M::Vm); let elements : integer = 64 DIV esize;

Assembler Symbols