This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

VCLZ -- AArch32

VCLZ

Vector Count Leading Zeros counts the number of consecutive zeros, starting from the most significant bit, in each element in a vector, and places the results in a second vector.

The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit integers. There is no distinction between signed and unsigned integers.

The result vector elements are the same data type as the operand vector elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11size00Vd01001QM0Vm
opc1opc2

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VCLZ{<c>}{<q>}.<dt> <Dd>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VCLZ{<c>}{<q>}.<dt> <Qd>, <Qm>

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

T1

15141312111098765432101514131211109876543210
111111111D11size00Vd01001QM0Vm
opc1opc2

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VCLZ{<c>}{<q>}.<dt> <Dd>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VCLZ{<c>}{<q>}.<dt> <Qd>, <Qm>

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

Assembler Symbols

<c>

For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1 128-bit SIMD vector" and "T1 64-bit SIMD vector" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the operands, encoded in size:

size <dt>
00 I8
01 I16
10 I32
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); for r = 0 to regs-1 do for e = 0 to elements-1 do D(d+r)[e*:esize] = CountLeadingZeroBits(D(m+r)[e*:esize])[esize-1:0]; end; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.