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VCVTT -- AArch32

VCVTT

Convert to or from a half-precision value in the top half of a single-precision register does one of the following:

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 111111101D11001opVd101sz11M0Vm
condo1T

Encoding for the Half-precision to single-precision variant

Applies when (op == 0 && sz == 0)

VCVTT{<c>}{<q>}.F32.F16 <Sd>, <Sm>

Encoding for the Half-precision to double-precision variant

Applies when (op == 0 && sz == 1)

VCVTT{<c>}{<q>}.F64.F16 <Dd>, <Sm>

Encoding for the Single-precision to half-precision variant

Applies when (op == 1 && sz == 0)

VCVTT{<c>}{<q>}.F16.F32 <Sd>, <Sm>

Encoding for the Double-precision to half-precision variant

Applies when (op == 1 && sz == 1)

VCVTT{<c>}{<q>}.F16.F64 <Sd>, <Dm>

Decode for all variants of this encoding

let d : integer = if sz == '1' && op == '0' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if sz == '1' && op == '1' then UInt(M::Vm) else UInt(Vm::M); let uses_double : boolean = (sz == '1'); let convert_from_half : boolean = (op == '0'); let lowbit : integer{} = (if T == '1' then 16 else 0);

T1

15141312111098765432101514131211109876543210
111011101D11001opVd101sz11M0Vm
o1T

Encoding for the Half-precision to single-precision variant

Applies when (op == 0 && sz == 0)

VCVTT{<c>}{<q>}.F32.F16 <Sd>, <Sm>

Encoding for the Half-precision to double-precision variant

Applies when (op == 0 && sz == 1)

VCVTT{<c>}{<q>}.F64.F16 <Dd>, <Sm>

Encoding for the Single-precision to half-precision variant

Applies when (op == 1 && sz == 0)

VCVTT{<c>}{<q>}.F16.F32 <Sd>, <Sm>

Encoding for the Double-precision to half-precision variant

Applies when (op == 1 && sz == 1)

VCVTT{<c>}{<q>}.F16.F64 <Sd>, <Dm>

Decode for all variants of this encoding

let d : integer = if sz == '1' && op == '0' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if sz == '1' && op == '1' then UInt(M::Vm) else UInt(Vm::M); let uses_double : boolean = (sz == '1'); let convert_from_half : boolean = (op == '0'); let lowbit : integer{} = (if T == '1' then 16 else 0);

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckVFPEnabled(TRUE); var hp : bits(16); let fpcr : FPCR_Type = EffectiveFPCR(); if convert_from_half then hp = S(m)[lowbit+15:lowbit]; if uses_double then D(d) = FPConvert{64, 16}(hp, fpcr); else S(d) = FPConvert{32, 16}(hp, fpcr); end; else if uses_double then hp = FPConvert{16, 64}(D(m), fpcr); else hp = FPConvert{16, 32}(S(m), fpcr); end; S(d)[lowbit+15:lowbit] = hp; end; end;


2026-03_rel 2026-03-26 20:48:11

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