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VNEG -- AArch32

VNEG

Vector Negate negates each element in a vector, and places the results in a second vector. The floating-point version only inverts the sign bit.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
111100111D11size01Vd0F111QM0Vm
opc1

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VNEG{<c>}{<q>}.<dt> <Dd>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VNEG{<c>}{<q>}.<dt> <Qd>, <Qm>

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if F == '1' && ((size == '01' && !IsFeatureImplemented(FEAT_FP16)) || size == '00') then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let advsimd : boolean = TRUE; let floating_point : boolean = (F == '1'); let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

A2

313029282726252423222120191817161514131211109876543210
!= 111111101D110001Vd10size01M0Vm
condo1opc2o3

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VNEG{<c>}{<q>}.F16 <Sd>, <Sm>

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VNEG{<c>}{<q>}.F32 <Sd>, <Sm>

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VNEG{<c>}{<q>}.F64 <Dd>, <Dm>

Decode for all variants of this encoding

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; if size == '01' && cond != '1110' then UnpredictableProcedure(); end; if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end; let advsimd : boolean = FALSE; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M); let floating_point : boolean = ARBITRARY : boolean; let regs : integer = ARBITRARY : integer; let elements : integer = ARBITRARY : integer;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && cond != '1110', then one of the following behaviors must occur:

T1

15141312111098765432101514131211109876543210
111111111D11size01Vd0F111QM0Vm
opc1

Encoding for the 64-bit SIMD vector variant

Applies when (Q == 0)

VNEG{<c>}{<q>}.<dt> <Dd>, <Dm>

Encoding for the 128-bit SIMD vector variant

Applies when (Q == 1)

VNEG{<c>}{<q>}.<dt> <Qd>, <Qm>

Decode for all variants of this encoding

if size == '11' then Undefined(); end; if F == '1' && ((size == '01' && !IsFeatureImplemented(FEAT_FP16)) || size == '00') then Undefined(); end; if F == '1' && size == '01' && InITBlock() then UnpredictableProcedure(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let advsimd : boolean = TRUE; let floating_point : boolean = (F == '1'); let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

CONSTRAINED UNPREDICTABLE behavior

If F == '1' && size == '01' && InITBlock(), then one of the following behaviors must occur:

T2

15141312111098765432101514131211109876543210
111011101D110001Vd10size01M0Vm
o1opc2o3

Encoding for the Half-precision scalar variant
(FEAT_FP16)

Applies when (size == 01)

VNEG{<c>}{<q>}.F16 <Sd>, <Sm>

Encoding for the Single-precision scalar variant

Applies when (size == 10)

VNEG{<c>}{<q>}.F32 <Sd>, <Sm>

Encoding for the Double-precision scalar variant

Applies when (size == 11)

VNEG{<c>}{<q>}.F64 <Dd>, <Dm>

Decode for all variants of this encoding

if size == '00' || (size == '01' && !IsFeatureImplemented(FEAT_FP16)) then Undefined(); end; if size == '01' && InITBlock() then UnpredictableProcedure(); end; if FPSCR().Len != '000' || FPSCR().Stride != '00' then Undefined(); end; let advsimd : boolean = FALSE; let esize : integer{} = 8 << UInt(size); let d : integer = if size == '11' then UInt(D::Vd) else UInt(Vd::D); let m : integer = if size == '11' then UInt(M::Vm) else UInt(Vm::M); let floating_point : boolean = ARBITRARY : boolean; let regs : integer = ARBITRARY : integer; let elements : integer = ARBITRARY : integer;

CONSTRAINED UNPREDICTABLE behavior

If size == '01' && InITBlock(), then one of the following behaviors must occur:

Assembler Symbols

<c>

For the "A1 128-bit SIMD vector" and "A1 64-bit SIMD vector" variants: see Standard assembler syntax fields. This encoding must be unconditional.

For the "A2 Double-precision scalar", "A2 Half-precision scalar", and "A2 Single-precision scalar" variants: see Standard assembler syntax fields.

For the "T1 128-bit SIMD vector", "T1 64-bit SIMD vector", "T2 Double-precision scalar", "T2 Half-precision scalar", and "T2 Single-precision scalar" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<dt>

Is the data type for the elements of the vectors, encoded in (F :: size):

F size <dt>
0 00 S8
0 01 S16
0 10 S32
1 01 F16
1 10 F32
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>

Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<Qd>

Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Sd>

Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>

Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd); if advsimd then // Advanced SIMD instruction let fpcr : FPCR_Type = StandardFPCR(); for r = 0 to regs-1 do for e = 0 to elements-1 do if floating_point then D(d+r)[e*:esize] = FPNeg{esize}(D(m+r)[e*:esize], fpcr); else let result : integer = -SInt(D(m+r)[e*:esize]); D(d+r)[e*:esize] = result[esize-1:0]; end; end; end; else // VFP instruction let fpcr : FPCR_Type = EffectiveFPCR(); case esize of when 16 => H(d) = FPNeg{16}(H(m), fpcr); when 32 => S(d) = FPNeg{32}(S(m), fpcr); when 64 => D(d) = FPNeg{64}(D(m), fpcr); end; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About the DIT bit.


2026-03_rel 2026-03-26 20:48:11

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