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VQRSHL

Vector Saturating Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.

For truncated results see VQSHL (register).

The first operand and result elements are the same data type, and can be any one of:

• 8-bit, 16-bit, 32-bit, or 64-bit signed integers.
• 8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

The second operand is a signed integer of the same size.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if Q == '1' && (Vd[0] == '1' || Vm[0] == '1' || Vn[0] == '1') then Undefined(); end; let unsigned : boolean = (U == '1'); let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let n : integer = UInt(N::Vn); let regs : integer = if Q == '0' then 1 else 2;

T1

Decode for all variants of this encoding

if Q == '1' && (Vd[0] == '1' || Vm[0] == '1' || Vn[0] == '1') then Undefined(); end; let unsigned : boolean = (U == '1'); let esize : integer{} = 8 << UInt(size); let elements : integer = 64 DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let n : integer = UInt(N::Vn); let regs : integer = if Q == '0' then 1 else 2;