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VQRSHRN, VQRSHRUN -- AArch32

VQRSHRN, VQRSHRUN

Vector Saturating Rounding Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an immediate value, and places the rounded results in a doubleword vector.

For truncated results, see VQSHRN and VQSHRUN.

The operand elements must all be the same size, and can be any one of:

The result elements are half the width of the operand elements. If the operand elements are signed, the results can be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

313029282726252423222120191817161514131211109876543210
1111001U1D!= 000xxxVd100op01M1Vm
imm6LQ

Encoding for the Signed result variant

Applies when (op == 1)

VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>

Encoding for the Unsigned result variant

Applies when (U == 1 && op == 0)

VQRSHRUN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>

Decode for all variants of this encoding

if imm6 == '000xxx' then See("Related encodings"); end; if U == '0' && op == '0' then See("VRSHRN"); end; if Vm[0] == '1' then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = (esize << 1) - UInt(imm6); let src_unsigned : boolean = (U == '1' && op == '1'); let dest_unsigned : boolean = (U == '1'); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

T1

15141312111098765432101514131211109876543210
111U11111D!= 000xxxVd100op01M1Vm
imm6LQ

Encoding for the Signed result variant

Applies when (op == 1)

VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>

Encoding for the Unsigned result variant

Applies when (U == 1 && op == 0)

VQRSHRUN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>

Decode for all variants of this encoding

if imm6 == '000xxx' then See("Related encodings"); end; if U == '0' && op == '0' then See("VRSHRN"); end; if Vm[0] == '1' then Undefined(); end; let esize : integer{} = 8 << HighestSetBitNZ(imm6[5:3]); let elements : integer = 64 DIV esize; let shift_amount : integer = (esize << 1) - UInt(imm6); let src_unsigned : boolean = (U == '1' && op == '1'); let dest_unsigned : boolean = (U == '1'); let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm);

Related encodings: See Advanced SIMD one register and modified immediate for the T32 instruction set, or Advanced SIMD one register and modified immediate for the A32 instruction set.

Assembler Symbols

<c>

For the "A1 Signed result" and "A1 Unsigned result" variants: see Standard assembler syntax fields. This encoding must be unconditional.

For the "T1 Signed result" and "T1 Unsigned result" variants: see Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

<type>

For the "A1 Signed result" and "T1 Signed result" variants: is the data type for the elements of the vectors, encoded in U:

U <type>
0 S
1 U

For the "A1 Unsigned result" and "T1 Unsigned result" variants: is S when "U" is 1, and is encoded in "U".

<size>

Is the data size for the elements of the vectors, encoded in imm6:

imm6 <size>
001xxx 16
01xxxx 32
1xxxxx 64
<Dd>

Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Qm>

Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<imm>

Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>.

Operation

if ConditionPassed() then EncodingSpecificOperations(); CheckAdvSIMDEnabled(); let round : boolean = TRUE; for e = 0 to elements-1 do let opelt : bits(2*esize) = Qin(m>>1)[e*:(2*esize)]; let element : integer = if src_unsigned then UInt(opelt) else SInt(opelt); let rshrn : integer = RShr(element, shift_amount, round); let (result, sat) : (bits(esize), boolean) = SatQ{esize}(rshrn, dest_unsigned); D(d)[e*:esize] = result; if sat then FPSCR().QC = '1'; end; end; end;


2026-03_rel 2026-03-26 20:48:11

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