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VREV32

Vector Reverse in words reverses the order of 8-bit or 16-bit elements in each word of the vector, and places the result in the corresponding destination vector.

There is no distinction between data types, other than size.

The following figure shows an example of the operation of VREV32 doubleword operations.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) .

A1

Decode for all variants of this encoding

if UInt(op)+UInt(size) >= 3 then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << UInt(size); let container_size : integer = 64 >> UInt(op); let containers : integer = 64 DIV container_size; let elements_per_container : integer = container_size DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;

T1

Decode for all variants of this encoding

if UInt(op)+UInt(size) >= 3 then Undefined(); end; if Q == '1' && (Vd[0] == '1' || Vm[0] == '1') then Undefined(); end; let esize : integer{} = 8 << UInt(size); let container_size : integer = 64 >> UInt(op); let containers : integer = 64 DIV container_size; let elements_per_container : integer = container_size DIV esize; let d : integer = UInt(D::Vd); let m : integer = UInt(M::Vm); let regs : integer = if Q == '0' then 1 else 2;