This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

WFE -- AArch32

WFE

Wait For Event is a hint instruction that indicates that the PE can enter a low-power state and remain there until a wakeup event occurs. Wakeup events include the event signaled as a result of executing the SEV instruction on any PE in the multiprocessor system. For more information, see Wait For Event and Send Event.

As described in Wait For Event and Send Event, the execution of a WFE instruction that would otherwise cause entry to a low-power state can be trapped to a higher Exception level, see HCR.TWE, SCR.TWE, and SCTLR.nTWE.

It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 and T2 ) .

A1

313029282726252423222120191817161514131211109876543210
!= 1111001100100000(1)(1)(1)(1)(0)(0)(0)(0)00000010
condRimm4imm12

Encoding

WFE{<c>}{<q>}

Decode for this encoding

// No additional decoding required

T1

1514131211109876543210
1011111100100000
hint

Encoding

WFE{<c>}{<q>}

Decode for this encoding

// No additional decoding required

T2

15141312111098765432101514131211109876543210
111100111010(1)(1)(1)(1)10(0)0(0)00000000010
hintoption

Encoding

WFE{<c>}.W

Decode for this encoding

// No additional decoding required

For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors.

Assembler Symbols

<c>

See Standard assembler syntax fields.

<q>

See Standard assembler syntax fields.

Operation

if ConditionPassed() then EncodingSpecificOperations(); if IsEventRegisterSet() then ClearEventRegister(); else if HaveEL(EL3) && EL3SDDUndefPriority() then // Check for traps described by the Secure Monitor. // If the trap is enabled, the instruction will be UNDEFINED because EDSCR.SDD is 1. AArch32_CheckForWFxTrap(EL3, WFxType_WFE); end; if PSTATE.EL == EL0 then // Check for traps described by the OS. AArch32_CheckForWFxTrap(EL1, WFxType_WFE); end; if PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() then // Check for traps described by the Hypervisor. AArch32_CheckForWFxTrap(EL2, WFxType_WFE); end; if HaveEL(EL3) && PSTATE.M != M32_Monitor then // Check for traps described by the Secure Monitor. AArch32_CheckForWFxTrap(EL3, WFxType_WFE); end; WaitForEvent(); end; end;


2026-03_rel 2026-03-26 20:48:11

Copyright © 2010-2026 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.