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DCIMVAC
AArch32 Registers
AArch64 Registers
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Proprietary Notice

DCIMVAC, Data Cache line Invalidate by VA to PoC

The DCIMVAC characteristics are:

Purpose

Invalidate data or unified cache line by virtual address to PoC.

Configuration

AArch32 System instruction DCIMVAC performs the same function as AArch64 System instruction DC IVAC.

This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to DCIMVAC are UNDEFINED.

Attributes

DCIMVAC is a 32-bit System instruction.

Field descriptions

313029282726252423222120191817161514131211109876543210
VA

VA, bits [31:0]

Virtual address to use. No alignment restrictions apply to this VA.

Executing DCIMVAC

It is IMPLEMENTATION DEFINED whether, when this instruction is executed, it can generate a watchpoint. If this instruction can generate a watchpoint this is prioritized in the same way as other watchpoints.

Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'AArch32 data cache maintenance instructions (DC*)'.

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b01110b01100b001

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if AArch32_TreatDCAsNOP(CacheOp_Invalidate, CacheOpScope_PoC) && !AArch32_CanTrapDC(CacheOp_Invalidate, CacheOpScope_PoC) then ExecuteAsNOP(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T7 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T7 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TPCP == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TPC == '1' then AArch32_TakeHypTrapException(0x03); else if AArch32_TreatDCAsNOP(CacheOp_Invalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch32_DC(R(t), CacheOp_Invalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL2 then if AArch32_TreatDCAsNOP(CacheOp_Invalidate, CacheOpScope_PoC) && !AArch32_CanTrapDC(CacheOp_Invalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else if AArch32_TreatDCAsNOP(CacheOp_Invalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch32_DC(R(t), CacheOp_Invalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL3 then if AArch32_TreatDCAsNOP(CacheOp_Invalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch32_DC(R(t), CacheOp_Invalidate, CacheOpScope_PoC); end; end;

AArch32 Registers
AArch64 Registers
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AArch64 Instructions
Index by Encoding
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2026-03-12 12:23:09, 2025-09_rel_asl1

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