DCISW

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DCISW, Data Cache line Invalidate by Set/Way

Purpose

Configuration

AArch32 System instruction DCISW performs the same function as AArch64 System instruction DC ISW.

This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to DCISW are UNDEFINED.

Attributes

Field descriptions

SetWay, bits [31:4]

Contains two fields:

Way, bits[31:32-A], the number of the way to operate on.
Set, bits[B-1:L], the number of the set to operate on.

Bits[L-1:4] are RES0.

A = Log₂(ASSOCIATIVITY), L = Log₂(LINELEN), B = (L + S), S = Log₂(NSETS).

ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.

Level, bits [3:1]

Bit [0]

Executing DCISW

If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:

The instruction is UNDEFINED
The instruction performs cache maintenance on one of:
- No cache lines.
- A single arbitrary cache line.
- Multiple arbitrary cache lines.

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b000	0b0111	0b0110	0b010

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T7 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T7 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TSW == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TSW == '1' then AArch32_TakeHypTrapException(0x03); else AArch32_DC(R(t), CacheOp_Invalidate, CacheOpScope_SetWay); end; elsif PSTATE.EL == EL2 then AArch32_DC(R(t), CacheOp_Invalidate, CacheOpScope_SetWay); elsif PSTATE.EL == EL3 then AArch32_DC(R(t), CacheOp_Invalidate, CacheOpScope_SetWay); end;

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SetWay																												Level			RES0