DSPSR2

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DSPSR2, Debug Saved Process State Register 2

Purpose

Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE.

Configuration

AArch32 System register DSPSR2 bits [31:0] are architecturally mapped to AArch64 System register DSPSR_EL0[63:32] when FEAT_Debugv8p9 is implemented.

This register is present only when FEAT_Debugv8p9 is implemented and FEAT_AA32 is implemented. Otherwise, direct accesses to DSPSR2 are UNDEFINED.

Attributes

Field descriptions

Bits [31:5]

UINJ, bit [4]
When FEAT_UINJ is implemented:

Inject Undefined Instruction exception. Set to the value of PSTATE.UINJ on entering Debug state, and copied to PSTATE.UINJ on exiting Debug state.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bits [3:2]

PPEND, bit [1]
When FEAT_SEBEP is implemented:

PMU Profiling exception pending bit. Set to the value of PSTATE.PPEND on entering Debug state, and conditionally copied to PSTATE.PPEND on exiting Debug state.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Bit [0]

Accessing DSPSR2

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b011	0b0100	0b0101	0b010

if !(IsFeatureImplemented(FEAT_Debugv8p9) && IsFeatureImplemented(FEAT_AA32)) then Undefined(); elsif !Halted() then Undefined(); else R(t) = DSPSR2(); end;

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coproc	opc1	CRn	CRm	opc2
0b1111	0b011	0b0100	0b0101	0b010

if !(IsFeatureImplemented(FEAT_Debugv8p9) && IsFeatureImplemented(FEAT_AA32)) then Undefined(); elsif !Halted() then Undefined(); else DSPSR2() = R(t); end;

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																											UINJ	RES0		PPEND	RES0

DSPSR2, Debug Saved Process State Register 2

Purpose

Configuration

Attributes

Field descriptions

Bits [31:5]

UINJ, bit [4]When FEAT_UINJ is implemented:

Otherwise:

Bits [3:2]

PPEND, bit [1]When FEAT_SEBEP is implemented:

Otherwise:

Bit [0]

Accessing DSPSR2

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

UINJ, bit [4]
When FEAT_UINJ is implemented:

PPEND, bit [1]
When FEAT_SEBEP is implemented: