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ICC_HPPIR1
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

ICC_HPPIR1, Interrupt Controller Highest Priority Pending Interrupt Register 1

The ICC_HPPIR1 characteristics are:

Purpose

Indicates the highest priority pending Group 1 interrupt on the CPU interface.

Configuration

AArch32 System register ICC_HPPIR1 bits [31:0] performs the same function as AArch64 System register ICC_HPPIR1_EL1[31:0].

This register is present only when FEAT_AA32EL1 is implemented and GICv3 is implemented. Otherwise, direct accesses to ICC_HPPIR1 are UNDEFINED.

Attributes

ICC_HPPIR1 is a 32-bit register.

Field descriptions

313029282726252423222120191817161514131211109876543210
RES0INTID

Bits [31:24]

Reserved, RES0.

INTID, bits [23:0]

The INTID of the highest priority pending interrupt, if that interrupt is observable at the current Security state and Exception level.

If the highest priority pending interrupt is not observable, this field contains a special INTID to indicate the reason. This special INTID can take the value 1023 only. For more information, see 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR.IDbits and ICC_MCTLR.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0.

Accessing ICC_HPPIR1

Accesses to this register use the following encodings in the System register encoding space:

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b11000b11000b010

if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_GICv3)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T12 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T12 == '1' then AArch32_TakeHypTrapException(0x03); elsif ICC_SRE().SRE == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && ICH_HCR_EL2().TALL1 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && ICH_HCR().TALL1 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().IMO == '1' then R(t) = ICV_HPPIR1(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().IMO == '1' then R(t) = ICV_HPPIR1(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && PSTATE.M != M32_Monitor && SCR().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; else R(t) = ICC_HPPIR1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then Undefined(); elsif ICC_HSRE().SRE == '0' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64EL3) && !ELUsingAArch32(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_AArch32SystemAccessTrap(EL3, 0x03); end; elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_AA32EL3) && ELUsingAArch32(EL3) && SCR().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch32_TakeMonitorTrapException(); end; else R(t) = ICC_HPPIR1(); end; elsif PSTATE.EL == EL3 then if ICC_MSRE().SRE == '0' then Undefined(); else R(t) = ICC_HPPIR1(); end; end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
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Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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