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ITLBIMVA
AArch32 Registers
AArch64 Registers
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Proprietary Notice

ITLBIMVA, Instruction TLB Invalidate by VA

The ITLBIMVA characteristics are:

Purpose

Invalidate all cached copies of translation table entries from instruction TLBs that meet the following requirements:

From the entries that match these requirements, the entries that are invalidated are required for the following translation regime:

The invalidation only applies to the PE that executes this System instruction.

Arm deprecates the use of this System instruction. It is only provided for backward compatibility with earlier versions of the Arm architecture.

Configuration

This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to ITLBIMVA are UNDEFINED.

Attributes

ITLBIMVA is a 32-bit System instruction.

Field descriptions

313029282726252423222120191817161514131211109876543210
VARES0ASID

VA, bits [31:12]

Virtual address to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.

Bits [11:8]

Reserved, RES0.

ASID, bits [7:0]

ASID value to match. Any TLB entries that match the ASID value and VA value will be affected by this System instruction.

Global TLB entries that match the VA value will be affected by this operation, regardless of the value of the ASID field.

Executing ITLBIMVA

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b10000b01010b001

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T8 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T8 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TTLB == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TTLB == '1' then AArch32_TakeHypTrapException(0x03); else if IsFeatureImplemented(FEAT_XS) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_HCX) && IsHCRXEL2Enabled() && HCRX_EL2().FnXS == '1' then AArch32_ITLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Any, TLBI_ExcludeXS, R(t)); else AArch32_ITLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R(t)); end; end; elsif PSTATE.EL == EL2 then AArch32_ITLBI_VA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R(t)); elsif PSTATE.EL == EL3 then AArch32_ITLBI_VA(SecurityStateAtEL(EL3), Regime_EL30, VMID_NONE, Broadcast_NSH, TLBILevel_Any, TLBI_AllAttr, R(t)); end;

AArch32 Registers
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2026-03-12 12:23:09, 2025-09_rel_asl1

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