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TLBIMVAALIS
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

TLBIMVAALIS, TLB Invalidate by VA, All ASID, Last level, Inner Shareable

The TLBIMVAALIS characteristics are:

Purpose

Invalidate all cached copies of translation table entries from TLBs that meet the following requirements:

From the entries that match these requirements, the entries that are invalidated are required for the following translation regime:

The invalidation applies to all PEs in the same Inner Shareable shareability domain as the PE that executes this System instruction.

Configuration

This instruction is present only when FEAT_AA32EL1 is implemented. Otherwise, direct accesses to TLBIMVAALIS are UNDEFINED.

Note

This System instruction is not implemented in architecture versions before Armv8.

Attributes

TLBIMVAALIS is a 32-bit System instruction.

Field descriptions

313029282726252423222120191817161514131211109876543210
VARES0

VA, bits [31:12]

Virtual address to match. Any unlocked TLB entries that match the VA will be affected by this System instruction, regardless of the ASID.

Bits [11:0]

Reserved, RES0.

Executing TLBIMVAALIS

Accesses to this instruction use the following encodings in the System instruction encoding space:

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}

coprocopc1CRnCRmopc2
0b11110b0000b10000b00110b111

if !IsFeatureImplemented(FEAT_AA32EL1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HSTR_EL2().T8 == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HSTR().T8 == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TTLB == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && HCR_EL2().TTLBIS == '1' then AArch64_AArch32SystemAccessTrap(EL2, 0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR().TTLB == '1' then AArch32_TakeHypTrapException(0x03); elsif EL2Enabled() && IsFeatureImplemented(FEAT_AA32EL2) && ELUsingAArch32(EL2) && HCR2().TTLBIS == '1' then AArch32_TakeHypTrapException(0x03); else if IsFeatureImplemented(FEAT_XS) && IsFeatureImplemented(FEAT_AA64EL2) && !ELUsingAArch32(EL2) && IsFeatureImplemented(FEAT_HCX) && IsHCRXEL2Enabled() && HCRX_EL2().FnXS == '1' then AArch32_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_ExcludeXS, R(t)); else AArch32_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_AllAttr, R(t)); end; end; elsif PSTATE.EL == EL2 then AArch32_TLBI_VAA(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_ISH, TLBILevel_Last, TLBI_AllAttr, R(t)); elsif PSTATE.EL == EL3 then AArch32_TLBI_VAA(SecurityStateAtEL(EL3), Regime_EL30, VMID_NONE, Broadcast_ISH, TLBILevel_Last, TLBI_AllAttr, R(t)); end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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