DC CGDVAC

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DC CGDVAC, Clean of Data and Allocation Tags by VA to PoC

Purpose

Configuration

This instruction is present only when FEAT_MTE is implemented. Otherwise, direct accesses to DC CGDVAC are UNDEFINED.

Attributes

Field descriptions

VA, bits [63:0]

Executing DC CGDVAC

If EL0 access is enabled, when executed at EL0, the instruction may generate a Permission fault, subject to the constraints described in 'MMU faults generated by cache maintenance operations'.

Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'.

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

DC CGDVAC, <Xt>

op0	op1	CRn	CRm	op2
0b01	0b011	0b0111	0b1010	0b101

if !IsFeatureImplemented(FEAT_MTE) then Undefined(); elsif PSTATE.EL == EL0 then if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) && !AArch64_CanTrapDC(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); elsif !ELIsInHost(EL0) && SCTLR_EL1().UCI == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCVAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2().UCI == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL1 then if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) && !AArch64_CanTrapDC(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); elsif EL2Enabled() && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCVAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL2 then if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) && !AArch64_CanTrapDC(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); else if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL3 then if AArch64_TreatDCAsNOP(CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data_Tag, CacheOp_Clean, CacheOpScope_PoC); end; end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VA
VA

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VA
VA

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VA
VA

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VA
VA