DC CSW

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DC CSW, Data or unified Cache line Clean by Set/Way

Purpose

Configuration

AArch64 System instruction DC CSW performs the same function as AArch32 System instruction DCCSW.

This instruction is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to DC CSW are UNDEFINED.

Attributes

Field descriptions

Bits [63:32]

SetWay, bits [31:4]

Contains two fields:

Way, bits[31:32-A], the number of the way to operate on.
Set, bits[B-1:L], the number of the set to operate on.

Bits[L-1:4] are RES0.

A = Log₂(ASSOCIATIVITY), L = Log₂(LINELEN), B = (L + S), S = Log₂(NSETS).

ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer.

Level, bits [3:1]

Bit [0]

Executing DC CSW

If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs:

The instruction is UNDEFINED.
The instruction performs cache maintenance on one of:
- No cache lines.
- A single arbitrary cache line.
- Multiple arbitrary cache lines.

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

DC CSW, <Xt>

op0	op1	CRn	CRm	op2
0b01	0b000	0b0111	0b1010	0b010

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TSW == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCSW == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay); end; elsif PSTATE.EL == EL2 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay); elsif PSTATE.EL == EL3 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
SetWay																												Level			RES0