ERXPFGCTL

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ERXPFGCTL_EL1, Selected Pseudo-fault Generation Control Register

Purpose

Configuration

This register is present only when FEAT_RASv1p1 is implemented. Otherwise, direct accesses to ERXPFGCTL_EL1 are UNDEFINED.

Attributes

Field descriptions

ERRnPFGCTL, bits [63:0]

Accessing ERXPFGCTL_EL1

If ERRIDR_EL1.NUM is 0x0000 or ERRSELR_EL1.SEL is greater than or equal to ERRIDR_EL1.NUM, then one of the following occurs:

An UNKNOWN error record is selected.
ERXPFGCTL_EL1 is RAZ/WI.
Direct reads and writes of ERXPFGCTL_EL1 are NOPs.
Direct reads and writes of ERXPFGCTL_EL1 are UNDEFINED.

If ERRSELR_EL1.SEL selects an error record owned by a node that does not implement the Common Fault Injection Model Extension, then one of the following occurs:

ERXPFGCTL_EL1 is RAZ/WI.
Direct reads and writes of ERXPFGCTL_EL1 are NOPs.
Direct reads and writes of ERXPFGCTL_EL1 are UNDEFINED.

Note

A node does not implement the Common Fault Injection Model Extension if ERR<q>FR.INJ reads as 0b00. <q> is the index of the first error record owned by the same node as error record <n>, where <n> is the value in ERRSELR_EL1.SEL. If the node owns a single record then q = n.

If ERRSELR_EL1.SEL is not the index of the first error record owned by a node, then ERR<n>PFGCTL is not present, meaning reads and writes of ERXPFGCTL_EL1 are RES0.

ERR<n>PFGCTL describes additional constraints that also apply when ERR<n>PFGCTL is accessed through ERXPFGCTL_EL1.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, ERXPFGCTL_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0101	0b0100	0b101

if !IsFeatureImplemented(FEAT_RASv1p1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FIEN == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().FIEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().ERXPFGCTL_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().FIEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ERXPFGCTL_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FIEN == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FIEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ERXPFGCTL_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = ERXPFGCTL_EL1(); end;

MSR ERXPFGCTL_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0101	0b0100	0b101

if !IsFeatureImplemented(FEAT_RASv1p1) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FIEN == '0' then Undefined(); elsif EL2Enabled() && HCR_EL2().FIEN == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().ERXPFGCTL_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().FIEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ERXPFGCTL_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FIEN == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FIEN == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ERXPFGCTL_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then ERXPFGCTL_EL1() = X{64}(t); end;

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ERRnPFGCTL
ERRnPFGCTL