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FPMR
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

FPMR, Floating-point Mode Register

The FPMR characteristics are:

Purpose

Controls behaviors of the FP8 instructions.

Configuration

This register is present only when FEAT_FPMR is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to FPMR are UNDEFINED.

A direct or indirect read of this register occurs in program order relative to a direct write of this register without explicit synchronization.

On entry to or exit from Streaming SVE mode, FPMR is set to 0.

Attributes

FPMR is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0LSCALE2
NSCALERES0LSCALEOSCOSMRES0F8DF8S2F8S1

Bits [63:38]

Reserved, RES0.

LSCALE2, bits [37:32]

Downscaling value for instructions that convert the second FP8 input data stream to other floating-point formats.

This value is an unsigned integer that is subtracted from the result exponent.

The reset behavior of this field is:

NSCALE, bits [31:24]

Scaling value for instructions that convert other floating-point formats to an FP8 format.

This value is a signed integer that is added to the operand exponent.

The reset behavior of this field is:

Bit [23]

Reserved, RES0.

LSCALE, bits [22:16]

Downscaling value.

This value is an unsigned integer that is subtracted from:

The reset behavior of this field is:

OSC, bit [15]

Overflow saturation for FP8 convert instructions. Specifies the result when a floating-point Overflow exception is detected.

OSCMeaning
0b0

Infinity or NaN is generated.

0b1

Maximum normal number is generated.

The reset behavior of this field is:

OSM, bit [14]

Overflow saturation for FP8 multiplication instructions. Specifies the result when a floating-point Overflow exception is detected.

OSMMeaning
0b0

Infinity is generated.

0b1

Maximum normal number is generated.

The reset behavior of this field is:

Bits [13:9]

Reserved, RES0.

F8D, bits [8:6]

Destination result format for instructions that convert other floating-point values to an FP8 format.

F8DMeaning
0b000

OFP8 E5M2 format.

0b001

OFP8 E4M3 format.

All other values are reserved.

Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries.

Additionally, FP8 instructions are permitted to set an FP8 result with an unsupported format to 0xFF and signal an Invalid Operation floating-point exception.

It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field.

For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8).

The reset behavior of this field is:

F8S2, bits [5:3]

Second FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats.

F8S2Meaning
0b000

OFP8 E5M2 format.

0b001

OFP8 E4M3 format.

All other values are reserved.

Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries.

Additionally FP8 instructions are permitted to treat FP8 input values with an unsupported format as a signaling NaN.

It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field.

For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8).

The reset behavior of this field is:

F8S1, bits [2:0]

First FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats.

F8S1Meaning
0b000

OFP8 E5M2 format.

0b001

OFP8 E4M3 format.

All other values are reserved.

Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries.

Additionally FP8 instructions are permitted to treat FP8 input values with an unsupported format as a signaling NaN.

It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field.

For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8).

The reset behavior of this field is:

Accessing FPMR

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, FPMR

op0op1CRnCRmop2
0b110b0110b01000b01000b010

if !(IsFeatureImplemented(FEAT_FPMR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && SCTLR_EL1().EnFPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif ELIsInHost(EL0) && SCTLR_EL2().EnFPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3().HXEn == '0') || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3().HXEn == '0') || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else X{64}(t) = FPMR(); end; end;

MSR FPMR, <Xt>

op0op1CRnCRmop2
0b110b0110b01000b01000b010

if !(IsFeatureImplemented(FEAT_FPMR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && SCTLR_EL1().EnFPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif ELIsInHost(EL0) && SCTLR_EL2().EnFPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3().HXEn == '0') || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && ((HaveEL(EL3) && SCR_EL3().HXEn == '0') || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else FPMR() = X{64}(t); end; end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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