FPSR

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

FPSR, Floating-point Status Register

Purpose

Configuration

AArch64 System register FPSR bits [31:27] are architecturally mapped to AArch32 System register FPSCR[31:27].

AArch64 System register FPSR bit [7] is architecturally mapped to AArch32 System register FPSCR[7].

AArch64 System register FPSR bits [4:0] are architecturally mapped to AArch32 System register FPSCR[4:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to FPSR are UNDEFINED.

On entry to or exit from Streaming SVE mode, FPSR.{IOC, DZC, OFC, UFC, IXC, IDC, QC} are set to 1 and the remaining bits are set to 0.

Attributes

Field descriptions

Bits [63:32]

N, bit [31]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

Z, bit [30]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

C, bit [29]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

V, bit [28]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

QC, bit [27]

Bits [26:8]

IDC, bit [7]

Bits [6:5]

IXC, bit [4]

Inexact cumulative floating-point exception bit. This bit is set to 1 to indicate that the Inexact floating-point exception has occurred since 0 was last written to this bit.

How scalar and Advanced SIMD floating-point instructions update this bit depends on the value of the FPCR.IXE bit. This bit is set to 1 to indicate a floating-point exception only if FPCR.IXE is 0.

The criteria for the Inexact floating-point exception to occur are affected by whether denormalized numbers are flushed to zero and by the value of the FPCR.AH bit. For more information, see 'Floating-point exceptions and exception traps'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

UFC, bit [3]

Underflow cumulative floating-point exception bit. This bit is set to 1 to indicate that the Underflow floating-point exception has occurred since 0 was last written to this bit.

How scalar and Advanced SIMD floating-point instructions update this bit depends on the value of the FPCR.UFE bit. This bit is set to 1 to indicate a floating-point exception only if FPCR.UFE is 0 or if flushing denormalized numbers to zero is enabled.

The criteria for the Underflow floating-point exception to occur are affected by whether denormalized numbers are flushed to zero and by the value of the FPCR.AH bit. For more information, see 'Floating-point exceptions and exception traps'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

OFC, bit [2]

DZC, bit [1]

IOC, bit [0]

Invalid Operation cumulative floating-point exception bit. This bit is set to 1 to indicate that the Invalid Operation floating-point exception has occurred since 0 was last written to this bit.

How scalar and Advanced SIMD floating-point instructions update this bit depends on the value of the FPCR.IOE bit. This bit is set to 1 to indicate a floating-point exception only if FPCR.IOE is 0.

The criteria for the Invalid Operation floating-point exception to occur are affected by the value of the FPCR.AH bit. For more information, see 'Floating-point exceptions and exception traps'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing FPSR

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, FPSR

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0100	0b001

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPSR(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPSR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPSR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else X{64}(t) = FPSR(); end; end;

MSR FPSR, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b011	0b0100	0b0100	0b001

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPSR() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPSR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPSR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else FPSR() = X{64}(t); end; end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
N	Z	C	V	QC	RES0																			IDC	RES0		IXC	UFC	OFC	DZC	IOC

FPSR, Floating-point Status Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:32]

N, bit [31]When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

Z, bit [30]When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

C, bit [29]When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

V, bit [28]When FEAT_AA32 is implemented and FEAT_FP is implemented:

Otherwise:

QC, bit [27]

Bits [26:8]

IDC, bit [7]

Bits [6:5]

IXC, bit [4]

UFC, bit [3]

OFC, bit [2]

DZC, bit [1]

IOC, bit [0]

Accessing FPSR

MRS <Xt>, FPSR

MSR FPSR, <Xt>

N, bit [31]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

Z, bit [30]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

C, bit [29]
When FEAT_AA32 is implemented and FEAT_FP is implemented:

V, bit [28]
When FEAT_AA32 is implemented and FEAT_FP is implemented: