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HFGWTR2_EL2
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

HFGWTR2_EL2, Hypervisor Fine-Grained Write Trap Register 2

The HFGWTR2_EL2 characteristics are:

Purpose

Provides controls for traps of MSRR, MSR and MCR writes of System registers.

Configuration

This register is present only when FEAT_FGT2 is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to HFGWTR2_EL2 are UNDEFINED.

If EL2 is not implemented, this register is RES0 from EL3.

Attributes

HFGWTR2_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0nACTLRALIAS_EL1nACTLRMASK_EL1nTCR2ALIAS_EL1nTCRALIAS_EL1nSCTLR2ALIAS_EL1nSCTLRALIAS_EL1nCPACRALIAS_EL1nTCR2MASK_EL1nTCRMASK_EL1nSCTLR2MASK_EL1nSCTLRMASK_EL1nCPACRMASK_EL1nRCWSMASK_EL1RES0nPFAR_EL1

Bits [63:15]

Reserved, RES0.

nACTLRALIAS_EL1, bit [14]
When FEAT_SRMASK is implemented:

Trap MSR writes of ACTLRALIAS_EL1 at EL1 using AArch64 to EL2.

nACTLRALIAS_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of ACTLRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of ACTLRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nACTLRMASK_EL1, bit [13]
When FEAT_SRMASK is implemented:

Trap MSR writes of ACTLRMASK_EL1 at EL1 using AArch64 to EL2.

nACTLRMASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of ACTLRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of ACTLRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nTCR2ALIAS_EL1, bit [12]
When FEAT_SRMASK is implemented:

Trap MSR writes of TCR2ALIAS_EL1 at EL1 using AArch64 to EL2.

nTCR2ALIAS_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of TCR2ALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of TCR2ALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nTCRALIAS_EL1, bit [11]
When FEAT_SRMASK is implemented:

Trap MSR writes of TCRALIAS_EL1 at EL1 using AArch64 to EL2.

nTCRALIAS_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of TCRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of TCRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSCTLR2ALIAS_EL1, bit [10]
When FEAT_SRMASK is implemented:

Trap MSR writes of SCTLR2ALIAS_EL1 at EL1 using AArch64 to EL2.

nSCTLR2ALIAS_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of SCTLR2ALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of SCTLR2ALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSCTLRALIAS_EL1, bit [9]
When FEAT_SRMASK is implemented:

Trap MSR writes of SCTLRALIAS_EL1 at EL1 using AArch64 to EL2.

nSCTLRALIAS_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of SCTLRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of SCTLRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nCPACRALIAS_EL1, bit [8]
When FEAT_SRMASK is implemented:

Trap MSR writes of CPACRALIAS_EL1 at EL1 using AArch64 to EL2.

nCPACRALIAS_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of CPACRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of CPACRALIAS_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nTCR2MASK_EL1, bit [7]
When FEAT_SRMASK is implemented:

Trap MSR writes of TCR2MASK_EL1 at EL1 using AArch64 to EL2.

nTCR2MASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of TCR2MASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of TCR2MASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nTCRMASK_EL1, bit [6]
When FEAT_SRMASK is implemented:

Trap MSR writes of TCRMASK_EL1 at EL1 using AArch64 to EL2.

nTCRMASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of TCRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of TCRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSCTLR2MASK_EL1, bit [5]
When FEAT_SRMASK is implemented:

Trap MSR writes of SCTLR2MASK_EL1 at EL1 using AArch64 to EL2.

nSCTLR2MASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of SCTLR2MASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of SCTLR2MASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nSCTLRMASK_EL1, bit [4]
When FEAT_SRMASK is implemented:

Trap MSR writes of SCTLRMASK_EL1 at EL1 using AArch64 to EL2.

nSCTLRMASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of SCTLRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of SCTLRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nCPACRMASK_EL1, bit [3]
When FEAT_SRMASK is implemented:

Trap MSR writes of CPACRMASK_EL1 at EL1 using AArch64 to EL2.

nCPACRMASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of CPACRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of CPACRMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

nRCWSMASK_EL1, bit [2]
When FEAT_THE is implemented:

Trap MSR or MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 to EL2.

nRCWSMASK_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then unless the write generates a higher priority exception:

  • MSR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18.
  • MSRR writes of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14.
0b1

MSR and MSRR writes of RCWSMASK_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Bit [1]

Reserved, RES0.

nPFAR_EL1, bit [0]
When FEAT_PFAR is implemented:

Trap MSR writes of PFAR_EL1 at EL1 using AArch64 to EL2.

nPFAR_EL1Meaning
0b0

If EL2 is implemented and enabled in the current Security state, then MSR writes of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception.

0b1

MSR writes of PFAR_EL1 are not trapped by this mechanism.

This field is ignored by the PE and treated as zero when all of the following are true:

The reset behavior of this field is:


Otherwise:

Reserved, RES0.

Accessing HFGWTR2_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, HFGWTR2_EL2

op0op1CRnCRmop2
0b110b1000b00110b00010b011

if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x2C8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGWTR2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGWTR2_EL2(); end;

MSR HFGWTR2_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b00110b00010b011

if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x2C8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGWTR2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGWTR2_EL2() = X{64}(t); end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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