This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

MPAMVPM6_EL2
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

MPAMVPM6_EL2, MPAM Virtual PARTID Mapping Register 6

The MPAMVPM6_EL2 characteristics are:

Purpose

MPAMVPM6_EL2 provides mappings from virtual PARTIDs 24 - 27 to physical PARTIDs.

MPAMIDR_EL1.VPMR_MAX field gives the index of the highest implemented MPAMVPM<n>_EL2 registers. VPMR_MAX can be as large as 7 (8 registers) or 32 virtual PARTIDs. If MPAMIDR_EL1.VPMR_MAX == 0, there is only a single MPAMVPM<n>_EL2 register, MPAMVPM0_EL2.

Virtual PARTID mapping is enabled by MPAMHCR_EL2.EL1_VPMEN for the PARTID in MPAM1_EL1 and by MPAMHCR_EL2.EL0_VPMEN for the PARTID in MPAM0_EL1.

A virtual-to-physical PARTID mapping entry, PhyPARTID<n>, is valid only when the MPAMVPMV_EL2.VPM_V bit in bit position n is set to 1.

Configuration

This register is present only when (FEAT_MPAMv0p1 is implemented or FEAT_MPAMv1p0 is implemented), MPAMIDR_EL1.HAS_HCR == 1, and UInt(MPAMIDR_EL1.VPMR_MAX) > 5. Otherwise, direct accesses to MPAMVPM6_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

Attributes

MPAMVPM6_EL2 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
PhyPARTID27PhyPARTID26
PhyPARTID25PhyPARTID24

PhyPARTID27, bits [63:48]

Virtual PARTID Mapping Entry for virtual PARTID 27. PhyPARTID27 gives the mapping of virtual PARTID 27 to a physical PARTID.

The reset behavior of this field is:

PhyPARTID26, bits [47:32]

Virtual PARTID Mapping Entry for virtual PARTID 26. PhyPARTID26 gives the mapping of virtual PARTID 26 to a physical PARTID.

The reset behavior of this field is:

PhyPARTID25, bits [31:16]

Virtual PARTID Mapping Entry for virtual PARTID 25. PhyPARTID25 gives the mapping of virtual PARTID 25 to a physical PARTID.

The reset behavior of this field is:

PhyPARTID24, bits [15:0]

Virtual PARTID Mapping Entry for virtual PARTID 24. PhyPARTID24 gives the mapping of virtual PARTID 24 to a physical PARTID.

The reset behavior of this field is:

Accessing MPAMVPM6_EL2

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, MPAMVPM6_EL2

op0op1CRnCRmop2
0b110b1000b10100b01100b110

if !((IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAMIDR_EL1().HAS_HCR == '1' && UInt(MPAMIDR_EL1().VPMR_MAX) > 5) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x970); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAM) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAM) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAM) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = MPAMVPM6_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = MPAMVPM6_EL2(); end;

MSR MPAMVPM6_EL2, <Xt>

op0op1CRnCRmop2
0b110b1000b10100b01100b110

if !((IsFeatureImplemented(FEAT_MPAMv0p1) || IsFeatureImplemented(FEAT_MPAMv1p0)) && MPAMIDR_EL1().HAS_HCR == '1' && UInt(MPAMIDR_EL1().VPMR_MAX) > 5) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x970) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then if HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAM) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else AArch64_SystemAccessTrap(EL2, 0x18); end; else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && IsFeatureImplemented(FEAT_MPAM) && MPAM3_EL3().TRAPLOWER == '1' then Undefined(); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_MPAM) && MPAM3_EL3().TRAPLOWER == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else MPAMVPM6_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then MPAMVPM6_EL2() = X{64}(t); end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.