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OSDLR_EL1

OSDLR_EL1, OS Double Lock Register

The OSDLR_EL1 characteristics are:

Purpose

Used to control the OS Double Lock.

Configuration

AArch64 System register OSDLR_EL1 bits [31:0] are architecturally mapped to AArch32 System register DBGOSDLR[31:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to OSDLR_EL1 are UNDEFINED.

Attributes

OSDLR_EL1 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
RES0
RES0DLK

Bits [63:1]

Reserved, RES0.

DLK, bit [0]
When FEAT_DoubleLock is implemented:

OS Double Lock control bit.

DLKMeaning
0b0

OS Double Lock unlocked.

0b1

OS Double Lock locked, if DBGPRCR_EL1.CORENPDRQ (Core no powerdown request) bit is set to 0 and the PE is in Non-debug state.

The reset behavior of this field is:


Otherwise:

Reserved, RAZ/WI.

Accessing OSDLR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, OSDLR_EL1

op0op1CRnCRmop2
0b100b0000b00010b00110b100

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_DoubleLock) && HDFGRTR_EL2().OSDLR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDOSA] != '00' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL2.TDOSA")) then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = OSDLR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = OSDLR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = OSDLR_EL1(); end;

MSR OSDLR_EL1, <Xt>

op0op1CRnCRmop2
0b100b0000b00010b00110b100

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && IsFeatureImplemented(FEAT_DoubleLock) && HDFGWTR_EL2().OSDLR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDOSA] != '00' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL2.TDOSA")) then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else OSDLR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TDOSA == '1' && (IsFeatureImplemented(FEAT_DoubleLock) || ImpDefBool("Trapped by MDCR_EL3.TDOSA")) then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else OSDLR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then OSDLR_EL1() = X{64}(t); end;


2026-03-12 12:23:09, 2025-09_rel_asl1

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