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SPMEVCNTR<n>_EL0
AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

SPMEVCNTR<n>_EL0, System Performance Monitors Event Count Register, n = 0 - 63

The SPMEVCNTR<n>_EL0 characteristics are:

Purpose

Event counter <n> in System PMU <s>, where n is 0 to 63.

Configuration

This register is present only when FEAT_SPMU is implemented and FEAT_AA64 is implemented. Otherwise, direct accesses to SPMEVCNTR<n>_EL0 are UNDEFINED.

Attributes

SPMEVCNTR<n>_EL0 is a 64-bit register.

Field descriptions

6362616059585756555453525150494847464544434241403938373635343332
313029282726252423222120191817161514131211109876543210
CNTR
CNTR

CNTR, bits [63:0]

Event counter n.

The number of implemented bits for SPMEVCNTR<n>_EL0 is IMPLEMENTATION DEFINED. Unimplemented bits are RES0.

The reset behavior of this field is:

Accessing SPMEVCNTR<n>_EL0

To access SPMEVCNTR<n>_EL0 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s and SPMSELR_EL0.BANK to n[5:4].

SPMEVCNTR<n>_EL0 reads-as-zero and ignores writes if any of the following are true:

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMEVCNTR<m>_EL0 ; Where m = 0-15

op0op1CRnCRmop2
0b100b0110b11100b000:m[3]m[2:0]

let m:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif MDSCR_EL1().EnSPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif !ELIsInHost(EL0) && SPMACCESSR_EL1()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; elsif PSTATE.EL == EL3 then if !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then X{64}(t) = Zeros{64}; else X{64}(t) = SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m); end; end;

MSR SPMEVCNTR<m>_EL0, <Xt> ; Where m = 0-15

op0op1CRnCRmop2
0b100b0110b11100b000:m[3]m[2:0]

let m:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then Undefined(); elsif MDSCR_EL1().EnSPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif !ELIsInHost(EL0) && SPMACCESSR_EL1()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMEVCNTRn_EL0 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if !IsSPMUCounterImplemented(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) then return; else SPMEVCNTR_EL0(UInt(SPMSELR_EL0().SYSPMUSEL), (UInt(SPMSELR_EL0().BANK) * 16) + m) = X{64}(t); end; end;

AArch32 Registers
AArch64 Registers
AArch32 Instructions
AArch64 Instructions
Index by Encoding
External Registers
External Registers by Offset
Registers by Functional Group
Proprietary Notice

2026-03-12 12:23:09, 2025-09_rel_asl1

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