SPMSCR

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SPMSCR_EL1, System Performance Monitors Secure Control Register

Purpose

Controls observability of Secure events by System PMU <s>, and optionally controls Secure attributes for message signaled interrupts and Non-secure access to the performance monitor registers.

Configuration

This register is present only when Secure EL1 is implemented, FEAT_SPMU is implemented, and FEAT_AA64 is implemented. Otherwise, direct accesses to SPMSCR_EL1 are UNDEFINED.

Attributes

Field descriptions

IMPLEMENTATION DEFINED, bits [63:32]

Bit [31]

Bits [30:5]

NAO, bit [4]
When System PMU <s> can count or monitor non-attributable events:

Non-attributable Observation. Controls whether events or monitorable characteristics not attributable with any source can be monitored by System PMU <s>.

NAO	Meaning
0b0	Events not attributable with any event source are not counted by System PMU <s>, unless overridden by SPMSCR_EL1.SO.
0b1	Counting non-attributable events by System PMU <s> is not prevented by this mechanism.

When both SPMROOTCR_EL3 and SPMSCR_EL1 are implemented, non-attributable events are counted only if both SPMROOTCR_EL3.NAO is 1 and SPMSCR_EL1.{NAO, SO} is nonzero.

SPMSCR_EL1.NAO has the opposite reset polarity to SPMROOTCR_EL3.NAO.

This field is optional if Root and Realm states are not implemented. When this field is not implemented, System PMU <s> behaves as if SPMSCR_EL1.NAO is 0, and whether events or monitorable characteristics not attributable with any source can be monitored is controlled by SPMSCR_EL1.SO.

The reset behavior of this field is:

On a System PMU reset, this field resets to '0'.

Otherwise:

Bits [3:1]

SO, bit [0]

SO	Meaning
0b0	Events attributable to a Secure event source are not counted by System PMU <s>.
0b1	Counting events by System PMU <s> that are attributable to a Secure event source is not prevented by this mechanism.

Accessing SPMSCR_EL1

To access SPMSCR_EL1 for System PMU <s>, set SPMSELR_EL0.SYSPMUSEL to s.

SPMSCR_EL1 reads-as-zero and ignores writes if any of the following are true:

System PMU <s> is not implemented.
System PMU <s> does not implement SPMSCR_EL1.

SPMSCR_EL1 is UNDEFINED if accessed in Non-secure or Realm state.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, SPMSCR_EL1

op0	op1	CRn	CRm	op2
0b10	0b111	0b1001	0b1110	0b111

if !(HaveELUsingSecurityState(EL1, TRUE) && IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif IsCurrentSecurityState(SS_NonSecure) || (IsFeatureImplemented(FEAT_RME) && IsCurrentSecurityState(SS_Realm)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGRTR2_EL2().nSPMSCR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMSCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] == '00' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = SPMSCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)); end; elsif PSTATE.EL == EL3 then X{64}(t) = SPMSCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)); end;

MSR SPMSCR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b10	0b111	0b1001	0b1110	0b111

if !(HaveELUsingSecurityState(EL1, TRUE) && IsFeatureImplemented(FEAT_SPMU) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif IsCurrentSecurityState(SS_NonSecure) || (IsFeatureImplemented(FEAT_RME) && IsCurrentSecurityState(SS_Realm)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HDFGWTR2_EL2().nSPMSCR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().EnSPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && SPMACCESSR_EL2()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SPMSCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().EnPM2 == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().EnPM2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) && SPMACCESSR_EL3()[UInt(SPMSELR_EL0().SYSPMUSEL) * 2+:2] != '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else SPMSCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t); end; elsif PSTATE.EL == EL3 then SPMSCR_EL1(UInt(SPMSELR_EL0().SYSPMUSEL)) = X{64}(t); end;

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED
RAO	RES0																										NAO	RES0			SO