TLBI VMALLS12E1, TLBI VMALLS12E1NXS

This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

TLBI VMALLS12E1, TLBI VMALLS12E1NXS, TLB Invalidate by VMID, All at Stage 1 and 2, EL1

Purpose

Invalidates cached copies of translation table entries from TLBs that meet all the following requirements:

If FEAT_XS is implemented, the nXS variant of this System instruction is defined.

It is IMPLEMENTATION SPECIFIC whether the TLBI System instruction with the nXS qualifier invalidates TLB entries with the XS attribute set to 1.

The TLBI System instruction without the nXS qualifier waits for all memory accesses using in-scope old translation information to complete before it is considered complete.

The TLBI System instruction with the nXS qualifier is considered complete when the subset of these memory accesses with XS attribute set to 0 are complete.

Configuration

This instruction is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to TLBI VMALLS12E1, TLBI VMALLS12E1NXS are UNDEFINED.

Attributes

Field descriptions

Executing TLBI VMALLS12E1, TLBI VMALLS12E1NXS

The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether:

The instruction is UNDEFINED.
The instruction behaves as if the Rt field is set to 0b11111.

This system instruction is an alias of the SYS instruction.

Accesses to this instruction use the following encodings in the System instruction encoding space:

TLBI VMALLS12E1{, <Xt>}

op0	op1	CRn	CRm	op2
0b01	0b100	0b1000	0b0111	0b110

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBI_AllAttr, X{64}(t)); elsif PSTATE.EL == EL3 then if !EL2Enabled() then AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_NSH, TLBI_AllAttr, X{64}(t)); else if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBI_AllAttr, X{64}(t)); end; end; end;

When FEAT_XS is implemented

TLBI VMALLS12E1NXS{, <Xt>}

op0	op1	CRn	CRm	op2
0b01	0b100	0b1001	0b0111	0b110

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif !IsFeatureImplemented(FEAT_XS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBI_ExcludeXS, X{64}(t)); elsif PSTATE.EL == EL3 then if !EL2Enabled() then AArch64_TLBI_VMALL(SecurityStateAtEL(EL1), Regime_EL10, VMID_NONE, Broadcast_NSH, TLBI_ExcludeXS, X{64}(t)); else if IsFeatureImplemented(FEAT_RME) && !ValidSecurityStateAtEL(EL1) then return; else AArch64_TLBI_VMALLS12(SecurityStateAtEL(EL1), Regime_EL10, VMID(), Broadcast_NSH, TLBI_ExcludeXS, X{64}(t)); end; end; end;