TPIDR_EL1

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TPIDR_EL1, EL1 Software Thread ID Register

Purpose

Provides a location where software executing at EL1 can store thread identifying information, for OS management purposes.

Configuration

AArch64 System register TPIDR_EL1 bits [31:0] are architecturally mapped to AArch32 System register TPIDRPRW[31:0].

This register is present only when FEAT_AA64 is implemented. Otherwise, direct accesses to TPIDR_EL1 are UNDEFINED.

Attributes

Field descriptions

ThreadID, bits [63:0]

Thread ID. Thread identifying information stored by software running at this Exception level.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing TPIDR_EL1

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TPIDR_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b1101	0b0000	0b100

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().TPIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = TPIDR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = TPIDR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = TPIDR_EL1(); end;

MSR TPIDR_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b1101	0b0000	0b100

if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().TPIDR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else TPIDR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then TPIDR_EL1() = X{64}(t); elsif PSTATE.EL == EL3 then TPIDR_EL1() = X{64}(t); end;

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ThreadID
ThreadID