AMCGCR

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AMCGCR, Activity Monitors Counter Group Configuration Register

Purpose

Provides information on the number of activity monitor event counters implemented within each counter group.

Configuration

External register AMCGCR bits [31:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[31:0] when FEAT_AMU_EXT32 is implemented.

External register AMCGCR bits [63:0] are architecturally mapped to AArch64 System register AMCGCR_EL0[63:0] when FEAT_AMU_EXT64 is implemented.

External register AMCGCR bits [31:0] are architecturally mapped to AArch32 System register AMCGCR[31:0].

It is IMPLEMENTATION DEFINED whether AMCGCR is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented and FEAT_AMU_EXT is implemented. Otherwise, direct accesses to AMCGCR are RES0.

Attributes

Field descriptions

When FEAT_AMU_EXT64 is implemented:

Bits [63:16]

CG1NC, bits [15:8]

Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.

In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CG0NC, bits [7:0]

Otherwise:

Bits [31:16]

CG1NC, bits [15:8]

Counter Group 1 Number of Counters. The number of counters in the auxiliary counter group.

In an implementation that includes FEAT_AMUv1, the permitted range of values is 0 to 16.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

CG0NC, bits [7:0]

Accessing AMCGCR

Accesses to this register use the following encodings:

When FEAT_AMU_EXT64 is implemented

Accessible at offset 0xCE0 from AMU

When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {0b001, 0b000}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {0b010, 0b000}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != 0b011, accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == 0, accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

When FEAT_AMU_EXT32 is implemented

Accessible at offset 0xCE0 from AMU

When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {0b001, 0b000}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {0b010, 0b000}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != 0b011, accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == 0, accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																CG1NC								CG0NC

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																CG1NC								CG0NC