AMPIDR1

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AMPIDR1, Activity Monitors Peripheral Identification Register 1

Purpose

Configuration

It is IMPLEMENTATION DEFINED whether AMPIDR1 is implemented in the Core power domain or in the Debug power domain.

This register is present only when FEAT_AMUv1 is implemented, an implementation implements AMPIDR1, and FEAT_AMU_EXT is implemented. Otherwise, direct accesses to AMPIDR1 are RES0.

Attributes

Field descriptions

Bits [31:8]

DES_0, bits [7:4]

Designer, least significant nibble of JEP106 ID code.

For Arm Limited, this field is 0b1011.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

PART_1, bits [3:0]

Part number, most significant nibble.

This field has an IMPLEMENTATION DEFINED value.

Access to this field is RO.

Accessing AMPIDR1

Accesses to this register use the following encodings:

Accessible at offset 0xFE4 from AMU

When ImpDefBool("AMU CoreSight management registers ignore access controls"), accesses to this register are RO.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Secure, and AMROOTCR().RA IN {0b001, 0b000}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Realm, and AMROOTCR().RA IN {0b010, 0b000}, accesses to this register are RAZ/WI.
When FEAT_RME is implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMROOTCR().RA != 0b011, accesses to this register are RAZ/WI.
When FEAT_RME is not implemented, FEAT_AMU_EXTACR is implemented, an access is Non-secure, and AMSCR().NSRA == 0, accesses to this register are RAZ/WI.
Otherwise, accesses to this register are RO.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																								DES_0				PART_1