This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

If you have a public document, related to the IA32® specifications and missing from the collection, please mail it to me. The content of this URL and all sub-ULRs is available for convenient bulk download by rsync x86docs password "" (empty).

EDCIDR0, External Debug Component Identification Register 0

The EDCIDR0 characteristics are:

Purpose

Provides information to identify an external debug component.

For more information, see 'About the Component Identification scheme'.

Configuration

When FEAT_DoPD is implemented, EDCIDR0 is in the Core power domain. Otherwise, EDCIDR0 is in the Debug power domain.

Implementation of this register is OPTIONAL.

This register is required for CoreSight compliance.

Attributes

EDCIDR0 is a 32-bit register.

Field descriptions

Bits [31:8]

PRMBL_0, bits [7:0]

Accessing EDCIDR0

EDCIDR0 can be accessed through the external debug interface:

Accessible as follows:

• When FEAT_DoPD is implemented and !IsCorePowered(), accesses to this register generate an error response.
• Otherwise, accesses to this register are RO.

2026-03-12 12:23:09, 2025-09_rel_asl1

Copyright © 2010-2025 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.