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ERRIMPDEF<n>

ERRIMPDEF<n>, IMPLEMENTATION DEFINED Register <n>, n = 0 - 191

The ERRIMPDEF<n> characteristics are:

Purpose

IMPLEMENTATION DEFINED RAS extensions.

Configuration

This register is present only when the Common Fault Injection Model Extension is not implemented, the Fault Injection Group is not implemented, ((FEAT_RASSA_4KB_GRP is implemented and UInt(ERRDEVID.NUM) <= 32), or (FEAT_RASSA_16KB_GRP is implemented and UInt(ERRDEVID.NUM) <= 128), or (FEAT_RASSA_64KB_GRP is implemented and UInt(ERRDEVID.NUM) <= 512)), and an implementation implements ERRIMPDEF<n>. Otherwise, direct accesses to ERRIMPDEF<n> are RES0.

Attributes

ERRIMPDEF<n> is a 64-bit register.

Field descriptions

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPLEMENTATION DEFINED
IMPLEMENTATION DEFINED

IMPLEMENTATION DEFINED, bits [63:0]

IMPLEMENTATION DEFINED.

Accessing ERRIMPDEF<n>

This section shows the offset of ERRIMPDEF<n> when FEAT_RASSA_4KB_GRP is implemented. If FEAT_RASSA_16KB_GRP or FEAT_RASSA_64KB_GRP is implemented, see 'RAS memory-mapped register views' for the offset of ERRIMPDEF<n>.

ERRIMPDEF<n> can be accessed through the memory-mapped interfaces:

Component	Offset	Instance
RAS	0x800 + (8 * n)	ERRIMPDEF<n>

Accesses to this register are RW.

2026-03-12 12:23:09, 2025-09_rel_asl1